6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 20:32:21 +00:00
Code Issues Projects Releases Wiki Activity

R600: Move trivial getters into header, use initializer list

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211917 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-06-27 17:57:00 +00:00
parent e70cdf9468
commit 896cde882f
2 changed files with 82 additions and 95 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

97
lib/Target/R600/AMDGPUSubtarget.cpp
View File

@ -25,25 +25,24 @@ using namespace llvm;
#define GET_SUBTARGETINFO_CTOR
#include "AMDGPUGenSubtargetInfo.inc"
AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
AMDGPUGenSubtargetInfo(TT, CPU, FS), DumpCode(false) {
InstrItins = getInstrItineraryForCPU(CPU);
// Default card
StringRef GPU = CPU;
Is64bit = false;
HasVertexCache = false;
TexVTXClauseSize = 0;
Gen = AMDGPUSubtarget::R600;
FP64 = false;
CaymanISA = false;
EnableIRStructurizer = true;
EnableIfCvt = true;
WavefrontSize = 0;
CFALUBug = false;
LocalMemorySize = 0;
AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS) :
AMDGPUGenSubtargetInfo(TT, GPU, FS),
DevName(GPU),
Is64bit(false),
DumpCode(false),
R600ALUInst(false),
HasVertexCache(false),
TexVTXClauseSize(0),
Gen(AMDGPUSubtarget::R600),
FP64(false),
CaymanISA(false),
EnableIRStructurizer(true),
EnableIfCvt(true),
WavefrontSize(0),
CFALUBug(false),
LocalMemorySize(0),
InstrItins(getInstrItineraryForCPU(GPU)) {
ParseSubtargetFeatures(GPU, FS);
DevName = GPU;
if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
InstrInfo.reset(new R600InstrInfo(*this));
@ -52,74 +51,16 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
}
}
bool
AMDGPUSubtarget::is64bit() const {
return Is64bit;
}
bool
AMDGPUSubtarget::hasVertexCache() const {
return HasVertexCache;
}
short
AMDGPUSubtarget::getTexVTXClauseSize() const {
return TexVTXClauseSize;
}
enum AMDGPUSubtarget::Generation
AMDGPUSubtarget::getGeneration() const {
return Gen;
}
bool
AMDGPUSubtarget::hasHWFP64() const {
return FP64;
}
bool
AMDGPUSubtarget::hasCaymanISA() const {
return CaymanISA;
}
bool
AMDGPUSubtarget::IsIRStructurizerEnabled() const {
return EnableIRStructurizer;
}
bool
AMDGPUSubtarget::isIfCvtEnabled() const {
return EnableIfCvt;
}
unsigned
AMDGPUSubtarget::getWavefrontSize() const {
return WavefrontSize;
}
unsigned
AMDGPUSubtarget::getStackEntrySize() const {
unsigned AMDGPUSubtarget::getStackEntrySize() const {
assert(getGeneration() <= NORTHERN_ISLANDS);
switch(getWavefrontSize()) {
case 16:
return 8;
case 32:
if (hasCaymanISA())
return 4;
else
return 8;
return hasCaymanISA() ? 4 : 8;
case 64:
return 4;
default:
llvm_unreachable("Illegal wavefront size.");
}
}
bool
AMDGPUSubtarget::hasCFAluBug() const {
assert(getGeneration() <= NORTHERN_ISLANDS);
return CFALUBug;
}
int
AMDGPUSubtarget::getLocalMemorySize() const {
return LocalMemorySize;
}
bool
AMDGPUSubtarget::isTargetELF() const {
return false;
}
std::string
AMDGPUSubtarget::getDeviceName() const {
return DevName;
}

80
lib/Target/R600/AMDGPUSubtarget.h
View File

@ -48,7 +48,7 @@ private:
bool R600ALUInst;
bool HasVertexCache;
short TexVTXClauseSize;
enum Generation Gen;
Generation Gen;
bool FP64;
bool CaymanISA;
bool EnableIRStructurizer;
@ -65,15 +65,36 @@ public:
const AMDGPUInstrInfo *getInstrInfo() const {
return InstrInfo.get();
}
const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
const InstrItineraryData &getInstrItineraryData() const {
return InstrItins;
}
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool is64bit() const;
bool hasVertexCache() const;
short getTexVTXClauseSize() const;
enum Generation getGeneration() const;
bool hasHWFP64() const;
bool hasCaymanISA() const;
bool is64bit() const {
return Is64bit;
}
bool hasVertexCache() const {
return HasVertexCache;
}
short getTexVTXClauseSize() const {
return TexVTXClauseSize;
}
Generation getGeneration() const {
return Gen;
}
bool hasHWFP64() const {
return FP64;
}
bool hasCaymanISA() const {
return CaymanISA;
}
bool hasBFE() const {
return (getGeneration() >= EVERGREEN);
@ -104,23 +125,48 @@ public:
hasCaymanISA());
}
bool IsIRStructurizerEnabled() const;
bool isIfCvtEnabled() const;
unsigned getWavefrontSize() const;
bool IsIRStructurizerEnabled() const {
return EnableIRStructurizer;
}
bool isIfCvtEnabled() const {
return EnableIfCvt;
}
unsigned getWavefrontSize() const {
return WavefrontSize;
}
unsigned getStackEntrySize() const;
bool hasCFAluBug() const;
int getLocalMemorySize() const;
bool hasCFAluBug() const {
assert(getGeneration() <= NORTHERN_ISLANDS);
return CFALUBug;
}
int getLocalMemorySize() const {
return LocalMemorySize;
}
bool enableMachineScheduler() const override {
return getGeneration() <= NORTHERN_ISLANDS;
}
// Helper functions to simplify if statements
bool isTargetELF() const;
std::string getDeviceName() const;
bool dumpCode() const { return DumpCode; }
bool r600ALUEncoding() const { return R600ALUInst; }
bool isTargetELF() const {
return false;
}
StringRef getDeviceName() const {
return DevName;
}
bool dumpCode() const {
return DumpCode;
}
bool r600ALUEncoding() const {
return R600ALUInst;
}
};
} // End namespace llvm