Rename llvm-uselistorder => verify-uselistorder

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214318 91177308-0d34-0410-b5e6-96231b3b80d8

test/Bitcode/2006-12-11-Cast-ConstExpr.ll

@@ -1,7 +1,7 @@
 ; This test ensures that we get a bitcast constant expression in and out,
 ; not a sitofp constant expression. 
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
-; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 ; CHECK: bitcast (
 
 @G = external global i32

test/Bitcode/2009-06-11-FirstClassAggregateConstant.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis -disable-output
-; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 ; PR4373
 
 @foo = weak global { i32 } zeroinitializer              

test/Bitcode/aggregateInstructions.3.2.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-dis < %s.bc| FileCheck %s
-; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; aggregateOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not misread instructions with aggregate operands

test/Bitcode/arm32_neon_vcnt_upgrade.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
-; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 ; Tests vclz and vcnt
 
 define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {

test/Bitcode/atomic.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-as %s -o - | llvm-dis | FileCheck %s
-; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 define void @test_cmpxchg(i32* %addr, i32 %desired, i32 %new) {
   cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst

test/Bitcode/attributes-3.3.ll

@@ -1,5 +1,5 @@
 ; RUN:  llvm-dis < %s.bc| FileCheck %s
-; RUN:  llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN:  verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; attributes-3.3.ll.bc was generated by passing this file to llvm-as-3.3.
 ; The test checks that LLVM does not silently misread attributes of

test/Bitcode/attributes.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
-; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 ; PR12696
 
 define void @f1(i8 zeroext)

test/Bitcode/binaryFloatInstructions.3.2.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-dis < %s.bc| FileCheck %s
-; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; BinaryFloatOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not misread binary float instructions from

test/Bitcode/binaryIntInstructions.3.2.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-dis < %s.bc| FileCheck %s
-; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; BinaryIntOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not misread binary integer instructions from

test/Bitcode/bitwiseInstructions.3.2.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-dis < %s.bc| FileCheck %s
-; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; bitwiseOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not misread bitwise instructions from

test/Bitcode/calling-conventions.3.2.ll

@@ -1,5 +1,5 @@
 ; RUN:  llvm-dis < %s.bc| FileCheck %s
-; RUN:  llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN:  verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; calling-conventions.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not silently misread calling conventions of

test/Bitcode/case-ranges-3.3.ll

@@ -1,5 +1,5 @@
 ; RUN:  llvm-dis < %s.bc| FileCheck %s
-; RUN:  llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN:  verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; case-ranges.ll.bc was generated by passing this file to llvm-as from the 3.3
 ; release of LLVM. This tests that the bitcode for switches from that release

test/Bitcode/cmpxchg-upgrade.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-dis < %s.bc | FileCheck %s
-; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; cmpxchg-upgrade.ll.bc was produced by running a version of llvm-as from just
 ; before the IR change on this file.

test/Bitcode/conversionInstructions.3.2.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-dis < %s.bc| FileCheck %s
-; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; conversionOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not misread conversion instructions from

test/Bitcode/drop-debug-info.ll

@@ -1,6 +1,6 @@
 ; RUN: llvm-as < %s -o %t.bc 2>&1 >/dev/null | FileCheck -check-prefix=WARN %s
 ; RUN: llvm-dis < %t.bc | FileCheck %s
-; RUN: llvm-uselistorder < %t.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %t.bc -preserve-bc-use-list-order -num-shuffles=5
 
 define i32 @main() {
 entry:

test/Bitcode/extractelement.ll

@@ -1,5 +1,5 @@
 ; RUN: opt < %s -constprop | llvm-dis -disable-output
-; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 ; PR3465
 
 define double @test() {

test/Bitcode/flags.ll

@@ -1,7 +1,7 @@
 ; RUN: llvm-as < %s | llvm-dis > %t0
 ; RUN: opt -S < %s > %t1
 ; RUN: diff %t0 %t1
-; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 ; PR6140
 
 ; Make sure the flags are serialized/deserialized properly for both

test/Bitcode/function-encoding-rel-operands.ll

@@ -1,7 +1,7 @@
 ; Basic sanity test to check that instruction operands are encoded with
 ; relative IDs.
 ; RUN: llvm-as < %s | llvm-bcanalyzer -dump | FileCheck %s
-; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 ; CHECK: FUNCTION_BLOCK
 ; CHECK: INST_BINOP {{.*}}op0=1 op1=1

test/Bitcode/global-variables.3.2.ll

@@ -1,5 +1,5 @@
 ; RUN:  llvm-dis < %s.bc| FileCheck %s
-; RUN:  llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN:  verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; global-variables.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not silently misread global variables attributes of

test/Bitcode/inalloca.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
-; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 ; inalloca should roundtrip.
 

test/Bitcode/linkage-types-3.2.ll

@@ -1,5 +1,5 @@
 ; RUN:  llvm-dis < %s.bc| FileCheck %s
-; RUN:  llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN:  verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; linkage-types-3.2.ll.bc was generated by passing this file to llvm-as-3.2
 ; The test checks that LLVM does not silently misread linkage types of

test/Bitcode/local-linkage-default-visibility.3.4.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-dis < %s.bc | FileCheck %s
-; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; local-linkage-default-visibility.3.4.ll.bc was generated by passing this file
 ; to llvm-as-3.4.  The test checks that LLVM upgrades visibility of symbols

test/Bitcode/memInstructions.3.2.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-dis < %s.bc| FileCheck %s
-; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; memOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not misread memory related instructions of

test/Bitcode/metadata.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis -disable-output
-; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 !llvm.foo = !{!0}
 !0 = metadata !{i32 42}

test/Bitcode/old-aliases.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-dis < %s.bc | FileCheck %s
-; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; old-aliases.bc consist of this file assembled with an old llvm-as (3.5 trunk)
 ; from when aliases contained a ConstantExpr.

test/Bitcode/ptest-new.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
-; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 define i32 @foo(<2 x i64> %bar) nounwind {
 entry:

test/Bitcode/ptest-old.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
-; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 define i32 @foo(<4 x float> %bar) nounwind {
 entry:

test/Bitcode/select.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
-; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 define <2 x i32> @main() {
   ret <2 x i32> select (<2 x i1> <i1 false, i1 undef>, <2 x i32> zeroinitializer, <2 x i32> <i32 0, i32 undef>)

test/Bitcode/shuffle.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis -disable-output
-; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 ; <rdar://problem/8622574>
 ; tests the bitcodereader can handle the case where the reader will initially

test/Bitcode/tailcall.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
-; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 ; Check that musttail and tail roundtrip.
 

test/Bitcode/terminatorInstructions.3.2.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-dis < %s.bc| FileCheck %s
-; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; TerminatorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not misread terminator instructions from

test/Bitcode/upgrade-global-ctors.ll

@@ -1,4 +1,4 @@
 ; RUN:  llvm-dis < %s.bc| FileCheck %s
-; RUN:  llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN:  verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; CHECK: @llvm.global_ctors = appending global [0 x { i32, void ()*, i8* }] zeroinitializer

test/Bitcode/upgrade-loop-metadata.ll

@@ -1,7 +1,7 @@
 ; Test to make sure loop vectorizer metadata is automatically upgraded.
 ;
 ; RUN: llvm-dis < %s.bc | FileCheck %s
-; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 define void @_Z28loop_with_vectorize_metadatav() {
 entry:

test/Bitcode/upgrade-tbaa.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
-; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 ; Function Attrs: nounwind
 define void @_Z4testPiPf(i32* nocapture %pI, float* nocapture %pF) #0 {

test/Bitcode/use-list-order.ll

@@ -1,4 +1,4 @@
-; RUN: llvm-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s -preserve-bc-use-list-order -num-shuffles=5
 
 @a = global [4 x i1] [i1 0, i1 1, i1 0, i1 1]
 @b = alias i1* getelementptr ([4 x i1]* @a, i64 0, i64 2)

test/Bitcode/vectorInstructions.3.2.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-dis < %s.bc| FileCheck %s
-; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; vectorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not misread vector operations of

test/Bitcode/visibility-styles.3.2.ll

@@ -1,5 +1,5 @@
 ; RUN:  llvm-dis < %s.bc| FileCheck %s
-; RUN:  llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN:  verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; visibility-styles.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not silently misread visibility styles of

test/Bitcode/weak-cmpxchg-upgrade.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-dis < %s.bc | FileCheck %s
-; RUN: llvm-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
+; RUN: verify-uselistorder < %s.bc -preserve-bc-use-list-order -num-shuffles=5
 
 ; cmpxchg-upgrade.ll.bc was produced by running a version of llvm-as from just
 ; before the IR change on this file.