Merging r224425:

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r224425 | tomatabacu | 2014-12-17 10:56:16 +0000 (Wed, 17 Dec 2014) | 17 lines

[mips] Set GCC-compatible MIPS asssembler options before inline asm blocks.

Summary:
When generating MIPS assembly, LLVM always overrides the default assembler options by emitting the '.set noreorder', '.set nomacro' and '.set noat' directives,
while GCC uses the default options if an assembly-level function contains inline assembly code.

This becomes a problem when the code generated by LLVM is interleaved with inline assembly which assumes GCC-like assembler options (from Linux, for example).

This patch fixes these conflicts by setting the appropriate assembler options at the beginning of an inline asm block and popping them at the end.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6637
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@231462 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2015-03-06 11:39:52 +00:00
parent 3682830c9e
commit 89ee039cd4
9 changed files with 64 additions and 31 deletions
-20
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@@ -1,20 +0,0 @@
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=static16
; Function Attrs: nounwind
define double @my_mul(double %a, double %b) #0 {
entry:
%a.addr = alloca double, align 8
%b.addr = alloca double, align 8
store double %a, double* %a.addr, align 8
store double %b, double* %b.addr, align 8
%0 = load double* %a.addr, align 8
%1 = load double* %b.addr, align 8
%mul = fmul double %0, %1
ret double %mul
}
; static16: .ent __fn_stub_my_mul
; static16: .set reorder
; static16-NEXT: #NO_APP
; static16: .end __fn_stub_my_mul
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" }
@@ -0,0 +1,23 @@
; RUN: llc -march=mips < %s | FileCheck %s
; Check for the emission of appropriate assembler directives before and
; after the inline assembly code.
define void @f() nounwind {
entry:
; CHECK: #APP
; CHECK-NEXT: .set push
; CHECK-NEXT: .set at
; CHECK-NEXT: .set macro
; CHECK-NEXT: .set reorder
; CHECK: addi $9, ${{[2-9][0-9]?}}, 8
; CHECK: subi ${{[2-9][0-9]?}}, $9, 6
; CHECK: .set pop
; CHECK-NEXT: #NO_APP
%a = alloca i32, align 4
%b = alloca i32, align 4
store i32 20, i32* %a, align 4
%0 = load i32* %a, align 4
%1 = call i32 asm sideeffect "addi $$9, $1, 8\0A\09subi $0, $$9, 6", "=r,r,~{$1}"(i32 %0)
store i32 %1, i32* %b, align 4
ret void
}
+3 -3
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@@ -32,10 +32,10 @@ entry:
; Now l with 1024: make sure register lo is picked. We do this by checking the instruction
; after the inline expression for a mflo to pull the value out of lo.
; CHECK: #APP
; CHECK-NEXT: mtlo ${{[0-9]+}}
; CHECK: #APP
; CHECK: mtlo ${{[0-9]+}}
; CHECK-NEXT: madd ${{[0-9]+}},${{[0-9]+}}
; CHECK-NEXT: #NO_APP
; CHECK: #NO_APP
; CHECK-NEXT: mflo ${{[0-9]+}}
%bosco = alloca i32, align 4
call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1,$2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind
+6 -4
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@@ -5,6 +5,7 @@
define i32 @f1(i32 %x) nounwind {
entry:
; CHECK-LABEL: f1:
; CHECK: addiu $[[T0:[0-9]+]], $sp
; CHECK: #APP
; CHECK: sw $4, 0($[[T0]])
@@ -22,17 +23,18 @@ entry:
ret i32 %0
}
; CHECK-LABEL: main:
; "D": Second word of double word. This works for any memory element
; double or single.
; CHECK: #APP
; CHECK-NEXT: lw ${{[0-9]+}},4(${{[0-9]+}});
; CHECK-NEXT: #NO_APP
; CHECK: lw ${{[0-9]+}},4(${{[0-9]+}});
; CHECK: #NO_APP
; No "D": First word of double word. This works for any memory element
; double or single.
; CHECK: #APP
; CHECK-NEXT: lw ${{[0-9]+}},0(${{[0-9]+}});
; CHECK-NEXT: #NO_APP
; CHECK: lw ${{[0-9]+}},0(${{[0-9]+}});
; CHECK: #NO_APP
;int b[8] = {0,1,2,3,4,5,6,7};
;int main()