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https://github.com/c64scene-ar/llvm-6502.git
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Merging r195716:
------------------------------------------------------------------------ r195716 | kevinqin | 2013-11-25 19:26:47 -0800 (Mon, 25 Nov 2013) | 3 lines Refactored the implementation of AArch64 NEON instruction ZIP, UZP and TRN. Fix a bug when mixed use of vget_high_u8() and vuzp_u8(). ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195735 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
9ed81d16f7
commit
8a0ff1f236
@ -921,6 +921,18 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
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return "AArch64ISD::NEON_REV32";
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case AArch64ISD::NEON_REV64:
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return "AArch64ISD::NEON_REV64";
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case AArch64ISD::NEON_UZP1:
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return "AArch64ISD::NEON_UZP1";
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case AArch64ISD::NEON_UZP2:
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return "AArch64ISD::NEON_UZP2";
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case AArch64ISD::NEON_ZIP1:
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return "AArch64ISD::NEON_ZIP1";
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case AArch64ISD::NEON_ZIP2:
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return "AArch64ISD::NEON_ZIP2";
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case AArch64ISD::NEON_TRN1:
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return "AArch64ISD::NEON_TRN1";
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case AArch64ISD::NEON_TRN2:
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return "AArch64ISD::NEON_TRN2";
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case AArch64ISD::NEON_LD1_UPD:
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return "AArch64ISD::NEON_LD1_UPD";
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case AArch64ISD::NEON_LD2_UPD:
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@ -3826,6 +3838,59 @@ AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
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return false;
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}
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// Check whether a Build Vector could be presented as Shuffle Vector. If yes,
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// try to call LowerVECTOR_SHUFFLE to lower it.
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bool AArch64TargetLowering::isKnownShuffleVector(SDValue Op, SelectionDAG &DAG,
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SDValue &Res) const {
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SDLoc DL(Op);
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EVT VT = Op.getValueType();
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unsigned NumElts = VT.getVectorNumElements();
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unsigned V0NumElts = 0;
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int Mask[16];
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SDValue V0, V1;
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// Check if all elements are extracted from less than 3 vectors.
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for (unsigned i = 0; i < NumElts; ++i) {
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SDValue Elt = Op.getOperand(i);
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if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
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return false;
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if (V0.getNode() == 0) {
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V0 = Elt.getOperand(0);
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V0NumElts = V0.getValueType().getVectorNumElements();
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}
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if (Elt.getOperand(0) == V0) {
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Mask[i] = (cast<ConstantSDNode>(Elt->getOperand(1))->getZExtValue());
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continue;
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} else if (V1.getNode() == 0) {
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V1 = Elt.getOperand(0);
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}
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if (Elt.getOperand(0) == V1) {
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unsigned Lane = cast<ConstantSDNode>(Elt->getOperand(1))->getZExtValue();
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Mask[i] = (Lane + V0NumElts);
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continue;
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} else {
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return false;
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}
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}
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if (!V1.getNode() && V0NumElts == NumElts * 2) {
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V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V0,
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DAG.getConstant(NumElts, MVT::i64));
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V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V0,
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DAG.getConstant(0, MVT::i64));
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V0NumElts = V0.getValueType().getVectorNumElements();
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}
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if (V1.getNode() && NumElts == V0NumElts &&
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V0NumElts == V1.getValueType().getVectorNumElements()) {
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SDValue Shuffle = DAG.getVectorShuffle(VT, DL, V0, V1, Mask);
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Res = LowerVECTOR_SHUFFLE(Shuffle, DAG);
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return true;
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} else
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return false;
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}
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// If this is a case we can't handle, return null and let the default
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// expansion code take care of it.
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SDValue
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@ -3964,7 +4029,7 @@ AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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SmallVector<SDValue, 3> Ops;
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Ops.push_back(N);
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Ops.push_back(Op.getOperand(I));
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Ops.push_back(DAG.getConstant(I, MVT::i32));
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Ops.push_back(DAG.getConstant(I, MVT::i64));
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N = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, &Ops[0], 3);
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}
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}
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@ -3980,6 +4045,11 @@ AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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if (isConstant)
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return SDValue();
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// Try to lower this in lowering ShuffleVector way.
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SDValue Shuf;
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if (isKnownShuffleVector(Op, DAG, Shuf))
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return Shuf;
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// If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
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// know the default expansion would otherwise fall back on something even
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// worse. For a vector with one or two non-undef values, that's
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@ -3992,7 +4062,7 @@ AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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SDValue V = Op.getOperand(i);
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if (V.getOpcode() == ISD::UNDEF)
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continue;
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SDValue LaneIdx = DAG.getConstant(i, MVT::i32);
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SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
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Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Vec, V, LaneIdx);
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}
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return Vec;
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@ -4030,6 +4100,83 @@ static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
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return true;
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}
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// isPermuteMask - Check whether the vector shuffle matches to UZP, ZIP and
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// TRN instruction.
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static unsigned isPermuteMask(ArrayRef<int> M, EVT VT) {
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unsigned NumElts = VT.getVectorNumElements();
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if (NumElts < 4)
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return 0;
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bool ismatch = true;
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// Check UZP1
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for (unsigned i = 0; i < NumElts; ++i) {
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if ((unsigned)M[i] != i * 2) {
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ismatch = false;
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break;
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}
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}
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if (ismatch)
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return AArch64ISD::NEON_UZP1;
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// Check UZP2
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ismatch = true;
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for (unsigned i = 0; i < NumElts; ++i) {
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if ((unsigned)M[i] != i * 2 + 1) {
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ismatch = false;
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break;
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}
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}
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if (ismatch)
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return AArch64ISD::NEON_UZP2;
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// Check ZIP1
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ismatch = true;
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for (unsigned i = 0; i < NumElts; ++i) {
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if ((unsigned)M[i] != i / 2 + NumElts * (i % 2)) {
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ismatch = false;
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break;
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}
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}
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if (ismatch)
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return AArch64ISD::NEON_ZIP1;
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// Check ZIP2
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ismatch = true;
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for (unsigned i = 0; i < NumElts; ++i) {
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if ((unsigned)M[i] != (NumElts + i) / 2 + NumElts * (i % 2)) {
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ismatch = false;
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break;
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}
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}
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if (ismatch)
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return AArch64ISD::NEON_ZIP2;
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// Check TRN1
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ismatch = true;
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for (unsigned i = 0; i < NumElts; ++i) {
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if ((unsigned)M[i] != i + (NumElts - 1) * (i % 2)) {
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ismatch = false;
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break;
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}
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}
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if (ismatch)
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return AArch64ISD::NEON_TRN1;
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// Check TRN2
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ismatch = true;
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for (unsigned i = 0; i < NumElts; ++i) {
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if ((unsigned)M[i] != 1 + i + (NumElts - 1) * (i % 2)) {
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ismatch = false;
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break;
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}
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}
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if (ismatch)
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return AArch64ISD::NEON_TRN2;
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return 0;
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}
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SDValue
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AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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SelectionDAG &DAG) const {
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@ -4056,6 +4203,10 @@ AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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if (isREVMask(ShuffleMask, VT, 16))
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return DAG.getNode(AArch64ISD::NEON_REV16, dl, VT, V1);
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unsigned ISDNo = isPermuteMask(ShuffleMask, VT);
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if (ISDNo)
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return DAG.getNode(ISDNo, dl, VT, V1, V2);
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// If the element of shuffle mask are all the same constant, we can
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// transform it into either NEON_VDUP or NEON_VDUPLANE
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if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
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@ -4167,10 +4318,12 @@ AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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else
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EltVT = (EltSize == 64) ? MVT::i64 : MVT::i32;
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ExtV = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, ExtV,
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DAG.getConstant(Mask, MVT::i64));
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InsV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, InsV, ExtV,
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DAG.getConstant(InsIndex[I], MVT::i64));
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if (Mask >= 0) {
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ExtV = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, ExtV,
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DAG.getConstant(Mask, MVT::i64));
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InsV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, InsV, ExtV,
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DAG.getConstant(InsIndex[I], MVT::i64));
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}
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}
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return InsV;
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}
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@ -125,6 +125,14 @@ namespace AArch64ISD {
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// Vector FP move immediate
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NEON_FMOVIMM,
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// Vector permute
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NEON_UZP1,
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NEON_UZP2,
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NEON_ZIP1,
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NEON_ZIP2,
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NEON_TRN1,
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NEON_TRN2,
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// Vector Element reverse
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NEON_REV64,
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NEON_REV32,
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@ -225,6 +233,8 @@ public:
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SDLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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bool isKnownShuffleVector(SDValue Op, SelectionDAG &DAG, SDValue &Res) const;
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SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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const AArch64Subtarget *ST) const;
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@ -46,6 +46,15 @@ def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
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def Neon_sqrshlImm : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
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def Neon_uqrshlImm : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
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def SDTPERMUTE : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
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SDTCisSameAs<0, 2>]>;
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def Neon_uzp1 : SDNode<"AArch64ISD::NEON_UZP1", SDTPERMUTE>;
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def Neon_uzp2 : SDNode<"AArch64ISD::NEON_UZP2", SDTPERMUTE>;
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def Neon_zip1 : SDNode<"AArch64ISD::NEON_ZIP1", SDTPERMUTE>;
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def Neon_zip2 : SDNode<"AArch64ISD::NEON_ZIP2", SDTPERMUTE>;
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def Neon_trn1 : SDNode<"AArch64ISD::NEON_TRN1", SDTPERMUTE>;
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def Neon_trn2 : SDNode<"AArch64ISD::NEON_TRN2", SDTPERMUTE>;
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def SDTVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
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def Neon_rev64 : SDNode<"AArch64ISD::NEON_REV64", SDTVSHUF>;
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def Neon_rev32 : SDNode<"AArch64ISD::NEON_REV32", SDTVSHUF>;
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@ -2384,331 +2393,57 @@ defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
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// The followings are for instruction class (Perm)
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class NeonI_Permute<bit q, bits<2> size, bits<3> opcode,
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string asmop, RegisterOperand OpVPR, string OpS>
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string asmop, RegisterOperand OpVPR, string OpS,
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SDPatternOperator opnode, ValueType Ty>
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: NeonI_Perm<q, size, opcode,
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(outs OpVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
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asmop # "\t$Rd." # OpS # ", $Rn." # OpS # ", $Rm." # OpS,
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[], NoItinerary>;
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[(set (Ty OpVPR:$Rd),
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(Ty (opnode (Ty OpVPR:$Rn), (Ty OpVPR:$Rm))))],
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NoItinerary>;
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multiclass NeonI_Perm_pat<bits<3> opcode, string asmop> {
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def _8b : NeonI_Permute<0b0, 0b00, opcode, asmop, VPR64, "8b">;
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def _16b : NeonI_Permute<0b1, 0b00, opcode, asmop, VPR128, "16b">;
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def _4h : NeonI_Permute<0b0, 0b01, opcode, asmop, VPR64, "4h">;
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def _8h : NeonI_Permute<0b1, 0b01, opcode, asmop, VPR128, "8h">;
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def _2s : NeonI_Permute<0b0, 0b10, opcode, asmop, VPR64, "2s">;
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def _4s : NeonI_Permute<0b1, 0b10, opcode, asmop, VPR128, "4s">;
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def _2d : NeonI_Permute<0b1, 0b11, opcode, asmop, VPR128, "2d">;
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}
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multiclass NeonI_Perm_pat<bits<3> opcode, string asmop,
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SDPatternOperator opnode> {
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def _8b : NeonI_Permute<0b0, 0b00, opcode, asmop,
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VPR64, "8b", opnode, v8i8>;
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def _16b : NeonI_Permute<0b1, 0b00, opcode, asmop,
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VPR128, "16b",opnode, v16i8>;
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def _4h : NeonI_Permute<0b0, 0b01, opcode, asmop,
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VPR64, "4h", opnode, v4i16>;
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def _8h : NeonI_Permute<0b1, 0b01, opcode, asmop,
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VPR128, "8h", opnode, v8i16>;
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def _2s : NeonI_Permute<0b0, 0b10, opcode, asmop,
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VPR64, "2s", opnode, v2i32>;
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def _4s : NeonI_Permute<0b1, 0b10, opcode, asmop,
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VPR128, "4s", opnode, v4i32>;
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def _2d : NeonI_Permute<0b1, 0b11, opcode, asmop,
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VPR128, "2d", opnode, v2i64>;
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}
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defm UZP1vvv : NeonI_Perm_pat<0b001, "uzp1">;
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defm TRN1vvv : NeonI_Perm_pat<0b010, "trn1">;
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defm ZIP1vvv : NeonI_Perm_pat<0b011, "zip1">;
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defm UZP2vvv : NeonI_Perm_pat<0b101, "uzp2">;
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defm TRN2vvv : NeonI_Perm_pat<0b110, "trn2">;
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defm ZIP2vvv : NeonI_Perm_pat<0b111, "zip2">;
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defm UZP1vvv : NeonI_Perm_pat<0b001, "uzp1", Neon_uzp1>;
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defm TRN1vvv : NeonI_Perm_pat<0b010, "trn1", Neon_trn1>;
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defm ZIP1vvv : NeonI_Perm_pat<0b011, "zip1", Neon_zip1>;
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defm UZP2vvv : NeonI_Perm_pat<0b101, "uzp2", Neon_uzp2>;
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defm TRN2vvv : NeonI_Perm_pat<0b110, "trn2", Neon_trn2>;
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defm ZIP2vvv : NeonI_Perm_pat<0b111, "zip2", Neon_zip2>;
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// Extract and Insert
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def NI_ei_i32 : PatFrag<(ops node:$Rn, node:$Rm, node:$Ext, node:$Ins),
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(vector_insert node:$Rn,
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(i32 (vector_extract node:$Rm, node:$Ext)),
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node:$Ins)>;
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multiclass NeonI_Perm_float_pat<string INS, SDPatternOperator opnode> {
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def : Pat<(v2f32 (opnode (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
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(!cast<Instruction>(INS # "_2s") VPR64:$Rn, VPR64:$Rm)>;
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def NI_ei_f32 : PatFrag<(ops node:$Rn, node:$Rm, node:$Ext, node:$Ins),
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(vector_insert node:$Rn,
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(f32 (vector_extract node:$Rm, node:$Ext)),
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node:$Ins)>;
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def : Pat<(v4f32 (opnode (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
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(!cast<Instruction>(INS # "_4s") VPR128:$Rn, VPR128:$Rm)>;
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// uzp1
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def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
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(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
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(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
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(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
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(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
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(v16i8 VPR128:$Rn),
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(v16i8 VPR128:$Rn), 2, 1)),
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(v16i8 VPR128:$Rn), 4, 2)),
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(v16i8 VPR128:$Rn), 6, 3)),
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(v16i8 VPR128:$Rn), 8, 4)),
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(v16i8 VPR128:$Rn), 10, 5)),
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(v16i8 VPR128:$Rn), 12, 6)),
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(v16i8 VPR128:$Rn), 14, 7)),
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(v16i8 VPR128:$Rm), 0, 8)),
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(v16i8 VPR128:$Rm), 2, 9)),
|
||||
(v16i8 VPR128:$Rm), 4, 10)),
|
||||
(v16i8 VPR128:$Rm), 6, 11)),
|
||||
(v16i8 VPR128:$Rm), 8, 12)),
|
||||
(v16i8 VPR128:$Rm), 10, 13)),
|
||||
(v16i8 VPR128:$Rm), 12, 14)),
|
||||
(v16i8 VPR128:$Rm), 14, 15)),
|
||||
(UZP1vvv_16b VPR128:$Rn, VPR128:$Rm)>;
|
||||
def : Pat<(v2f64 (opnode (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
|
||||
(!cast<Instruction>(INS # "_2d") VPR128:$Rn, VPR128:$Rm)>;
|
||||
}
|
||||
|
||||
class NI_Uzp1_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
|
||||
: Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
|
||||
(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
|
||||
(Ty VPR:$Rn),
|
||||
(Ty VPR:$Rn), 2, 1)),
|
||||
(Ty VPR:$Rn), 4, 2)),
|
||||
(Ty VPR:$Rn), 6, 3)),
|
||||
(Ty VPR:$Rm), 0, 4)),
|
||||
(Ty VPR:$Rm), 2, 5)),
|
||||
(Ty VPR:$Rm), 4, 6)),
|
||||
(Ty VPR:$Rm), 6, 7)),
|
||||
(INST VPR:$Rn, VPR:$Rm)>;
|
||||
|
||||
def : NI_Uzp1_v8<v8i8, VPR64, UZP1vvv_8b>;
|
||||
def : NI_Uzp1_v8<v8i16, VPR128, UZP1vvv_8h>;
|
||||
|
||||
class NI_Uzp1_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
|
||||
PatFrag ei>
|
||||
: Pat<(Ty (ei (Ty (ei (Ty (ei
|
||||
(Ty VPR:$Rn),
|
||||
(Ty VPR:$Rn), 2, 1)),
|
||||
(Ty VPR:$Rm), 0, 2)),
|
||||
(Ty VPR:$Rm), 2, 3)),
|
||||
(INST VPR:$Rn, VPR:$Rm)>;
|
||||
|
||||
def : NI_Uzp1_v4<v4i16, VPR64, UZP1vvv_4h, NI_ei_i32>;
|
||||
def : NI_Uzp1_v4<v4i32, VPR128, UZP1vvv_4s, NI_ei_i32>;
|
||||
def : NI_Uzp1_v4<v4f32, VPR128, UZP1vvv_4s, NI_ei_f32>;
|
||||
|
||||
// uzp2
|
||||
def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 VPR128:$Rm),
|
||||
(v16i8 VPR128:$Rn), 1, 0)),
|
||||
(v16i8 VPR128:$Rn), 3, 1)),
|
||||
(v16i8 VPR128:$Rn), 5, 2)),
|
||||
(v16i8 VPR128:$Rn), 7, 3)),
|
||||
(v16i8 VPR128:$Rn), 9, 4)),
|
||||
(v16i8 VPR128:$Rn), 11, 5)),
|
||||
(v16i8 VPR128:$Rn), 13, 6)),
|
||||
(v16i8 VPR128:$Rn), 15, 7)),
|
||||
(v16i8 VPR128:$Rm), 1, 8)),
|
||||
(v16i8 VPR128:$Rm), 3, 9)),
|
||||
(v16i8 VPR128:$Rm), 5, 10)),
|
||||
(v16i8 VPR128:$Rm), 7, 11)),
|
||||
(v16i8 VPR128:$Rm), 9, 12)),
|
||||
(v16i8 VPR128:$Rm), 11, 13)),
|
||||
(v16i8 VPR128:$Rm), 13, 14)),
|
||||
(UZP2vvv_16b VPR128:$Rn, VPR128:$Rm)>;
|
||||
|
||||
class NI_Uzp2_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
|
||||
: Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
|
||||
(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
|
||||
(Ty VPR:$Rm),
|
||||
(Ty VPR:$Rn), 1, 0)),
|
||||
(Ty VPR:$Rn), 3, 1)),
|
||||
(Ty VPR:$Rn), 5, 2)),
|
||||
(Ty VPR:$Rn), 7, 3)),
|
||||
(Ty VPR:$Rm), 1, 4)),
|
||||
(Ty VPR:$Rm), 3, 5)),
|
||||
(Ty VPR:$Rm), 5, 6)),
|
||||
(INST VPR:$Rn, VPR:$Rm)>;
|
||||
|
||||
def : NI_Uzp2_v8<v8i8, VPR64, UZP2vvv_8b>;
|
||||
def : NI_Uzp2_v8<v8i16, VPR128, UZP2vvv_8h>;
|
||||
|
||||
class NI_Uzp2_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
|
||||
PatFrag ei>
|
||||
: Pat<(Ty (ei (Ty (ei (Ty (ei
|
||||
(Ty VPR:$Rm),
|
||||
(Ty VPR:$Rn), 1, 0)),
|
||||
(Ty VPR:$Rn), 3, 1)),
|
||||
(Ty VPR:$Rm), 1, 2)),
|
||||
(INST VPR:$Rn, VPR:$Rm)>;
|
||||
|
||||
def : NI_Uzp2_v4<v4i16, VPR64, UZP2vvv_4h, NI_ei_i32>;
|
||||
def : NI_Uzp2_v4<v4i32, VPR128, UZP2vvv_4s, NI_ei_i32>;
|
||||
def : NI_Uzp2_v4<v4f32, VPR128, UZP2vvv_4s, NI_ei_f32>;
|
||||
|
||||
// zip1
|
||||
def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 VPR128:$Rn),
|
||||
(v16i8 VPR128:$Rm), 0, 1)),
|
||||
(v16i8 VPR128:$Rn), 1, 2)),
|
||||
(v16i8 VPR128:$Rm), 1, 3)),
|
||||
(v16i8 VPR128:$Rn), 2, 4)),
|
||||
(v16i8 VPR128:$Rm), 2, 5)),
|
||||
(v16i8 VPR128:$Rn), 3, 6)),
|
||||
(v16i8 VPR128:$Rm), 3, 7)),
|
||||
(v16i8 VPR128:$Rn), 4, 8)),
|
||||
(v16i8 VPR128:$Rm), 4, 9)),
|
||||
(v16i8 VPR128:$Rn), 5, 10)),
|
||||
(v16i8 VPR128:$Rm), 5, 11)),
|
||||
(v16i8 VPR128:$Rn), 6, 12)),
|
||||
(v16i8 VPR128:$Rm), 6, 13)),
|
||||
(v16i8 VPR128:$Rn), 7, 14)),
|
||||
(v16i8 VPR128:$Rm), 7, 15)),
|
||||
(ZIP1vvv_16b VPR128:$Rn, VPR128:$Rm)>;
|
||||
|
||||
class NI_Zip1_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
|
||||
: Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
|
||||
(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
|
||||
(Ty VPR:$Rn),
|
||||
(Ty VPR:$Rm), 0, 1)),
|
||||
(Ty VPR:$Rn), 1, 2)),
|
||||
(Ty VPR:$Rm), 1, 3)),
|
||||
(Ty VPR:$Rn), 2, 4)),
|
||||
(Ty VPR:$Rm), 2, 5)),
|
||||
(Ty VPR:$Rn), 3, 6)),
|
||||
(Ty VPR:$Rm), 3, 7)),
|
||||
(INST VPR:$Rn, VPR:$Rm)>;
|
||||
|
||||
def : NI_Zip1_v8<v8i8, VPR64, ZIP1vvv_8b>;
|
||||
def : NI_Zip1_v8<v8i16, VPR128, ZIP1vvv_8h>;
|
||||
|
||||
class NI_Zip1_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
|
||||
PatFrag ei>
|
||||
: Pat<(Ty (ei (Ty (ei (Ty (ei
|
||||
(Ty VPR:$Rn),
|
||||
(Ty VPR:$Rm), 0, 1)),
|
||||
(Ty VPR:$Rn), 1, 2)),
|
||||
(Ty VPR:$Rm), 1, 3)),
|
||||
(INST VPR:$Rn, VPR:$Rm)>;
|
||||
|
||||
def : NI_Zip1_v4<v4i16, VPR64, ZIP1vvv_4h, NI_ei_i32>;
|
||||
def : NI_Zip1_v4<v4i32, VPR128, ZIP1vvv_4s, NI_ei_i32>;
|
||||
def : NI_Zip1_v4<v4f32, VPR128, ZIP1vvv_4s, NI_ei_f32>;
|
||||
|
||||
// zip2
|
||||
def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 VPR128:$Rm),
|
||||
(v16i8 VPR128:$Rn), 8, 0)),
|
||||
(v16i8 VPR128:$Rm), 8, 1)),
|
||||
(v16i8 VPR128:$Rn), 9, 2)),
|
||||
(v16i8 VPR128:$Rm), 9, 3)),
|
||||
(v16i8 VPR128:$Rn), 10, 4)),
|
||||
(v16i8 VPR128:$Rm), 10, 5)),
|
||||
(v16i8 VPR128:$Rn), 11, 6)),
|
||||
(v16i8 VPR128:$Rm), 11, 7)),
|
||||
(v16i8 VPR128:$Rn), 12, 8)),
|
||||
(v16i8 VPR128:$Rm), 12, 9)),
|
||||
(v16i8 VPR128:$Rn), 13, 10)),
|
||||
(v16i8 VPR128:$Rm), 13, 11)),
|
||||
(v16i8 VPR128:$Rn), 14, 12)),
|
||||
(v16i8 VPR128:$Rm), 14, 13)),
|
||||
(v16i8 VPR128:$Rn), 15, 14)),
|
||||
(ZIP2vvv_16b VPR128:$Rn, VPR128:$Rm)>;
|
||||
|
||||
class NI_Zip2_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
|
||||
: Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
|
||||
(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
|
||||
(Ty VPR:$Rm),
|
||||
(Ty VPR:$Rn), 4, 0)),
|
||||
(Ty VPR:$Rm), 4, 1)),
|
||||
(Ty VPR:$Rn), 5, 2)),
|
||||
(Ty VPR:$Rm), 5, 3)),
|
||||
(Ty VPR:$Rn), 6, 4)),
|
||||
(Ty VPR:$Rm), 6, 5)),
|
||||
(Ty VPR:$Rn), 7, 6)),
|
||||
(INST VPR:$Rn, VPR:$Rm)>;
|
||||
|
||||
def : NI_Zip2_v8<v8i8, VPR64, ZIP2vvv_8b>;
|
||||
def : NI_Zip2_v8<v8i16, VPR128, ZIP2vvv_8h>;
|
||||
|
||||
class NI_Zip2_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
|
||||
PatFrag ei>
|
||||
: Pat<(Ty (ei (Ty (ei (Ty (ei
|
||||
(Ty VPR:$Rm),
|
||||
(Ty VPR:$Rn), 2, 0)),
|
||||
(Ty VPR:$Rm), 2, 1)),
|
||||
(Ty VPR:$Rn), 3, 2)),
|
||||
(INST VPR:$Rn, VPR:$Rm)>;
|
||||
|
||||
def : NI_Zip2_v4<v4i16, VPR64, ZIP2vvv_4h, NI_ei_i32>;
|
||||
def : NI_Zip2_v4<v4i32, VPR128, ZIP2vvv_4s, NI_ei_i32>;
|
||||
def : NI_Zip2_v4<v4f32, VPR128, ZIP2vvv_4s, NI_ei_f32>;
|
||||
|
||||
// trn1
|
||||
def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 VPR128:$Rn),
|
||||
(v16i8 VPR128:$Rm), 0, 1)),
|
||||
(v16i8 VPR128:$Rm), 2, 3)),
|
||||
(v16i8 VPR128:$Rm), 4, 5)),
|
||||
(v16i8 VPR128:$Rm), 6, 7)),
|
||||
(v16i8 VPR128:$Rm), 8, 9)),
|
||||
(v16i8 VPR128:$Rm), 10, 11)),
|
||||
(v16i8 VPR128:$Rm), 12, 13)),
|
||||
(v16i8 VPR128:$Rm), 14, 15)),
|
||||
(TRN1vvv_16b VPR128:$Rn, VPR128:$Rm)>;
|
||||
|
||||
class NI_Trn1_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
|
||||
: Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
|
||||
(Ty VPR:$Rn),
|
||||
(Ty VPR:$Rm), 0, 1)),
|
||||
(Ty VPR:$Rm), 2, 3)),
|
||||
(Ty VPR:$Rm), 4, 5)),
|
||||
(Ty VPR:$Rm), 6, 7)),
|
||||
(INST VPR:$Rn, VPR:$Rm)>;
|
||||
|
||||
def : NI_Trn1_v8<v8i8, VPR64, TRN1vvv_8b>;
|
||||
def : NI_Trn1_v8<v8i16, VPR128, TRN1vvv_8h>;
|
||||
|
||||
class NI_Trn1_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
|
||||
PatFrag ei>
|
||||
: Pat<(Ty (ei (Ty (ei
|
||||
(Ty VPR:$Rn),
|
||||
(Ty VPR:$Rm), 0, 1)),
|
||||
(Ty VPR:$Rm), 2, 3)),
|
||||
(INST VPR:$Rn, VPR:$Rm)>;
|
||||
|
||||
def : NI_Trn1_v4<v4i16, VPR64, TRN1vvv_4h, NI_ei_i32>;
|
||||
def : NI_Trn1_v4<v4i32, VPR128, TRN1vvv_4s, NI_ei_i32>;
|
||||
def : NI_Trn1_v4<v4f32, VPR128, TRN1vvv_4s, NI_ei_f32>;
|
||||
|
||||
// trn2
|
||||
def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
|
||||
(v16i8 VPR128:$Rm),
|
||||
(v16i8 VPR128:$Rn), 1, 0)),
|
||||
(v16i8 VPR128:$Rn), 3, 2)),
|
||||
(v16i8 VPR128:$Rn), 5, 4)),
|
||||
(v16i8 VPR128:$Rn), 7, 6)),
|
||||
(v16i8 VPR128:$Rn), 9, 8)),
|
||||
(v16i8 VPR128:$Rn), 11, 10)),
|
||||
(v16i8 VPR128:$Rn), 13, 12)),
|
||||
(v16i8 VPR128:$Rn), 15, 14)),
|
||||
(TRN2vvv_16b VPR128:$Rn, VPR128:$Rm)>;
|
||||
|
||||
class NI_Trn2_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
|
||||
: Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
|
||||
(Ty VPR:$Rm),
|
||||
(Ty VPR:$Rn), 1, 0)),
|
||||
(Ty VPR:$Rn), 3, 2)),
|
||||
(Ty VPR:$Rn), 5, 4)),
|
||||
(Ty VPR:$Rn), 7, 6)),
|
||||
(INST VPR:$Rn, VPR:$Rm)>;
|
||||
|
||||
def : NI_Trn2_v8<v8i8, VPR64, TRN2vvv_8b>;
|
||||
def : NI_Trn2_v8<v8i16, VPR128, TRN2vvv_8h>;
|
||||
|
||||
class NI_Trn2_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
|
||||
PatFrag ei>
|
||||
: Pat<(Ty (ei (Ty (ei
|
||||
(Ty VPR:$Rm),
|
||||
(Ty VPR:$Rn), 1, 0)),
|
||||
(Ty VPR:$Rn), 3, 2)),
|
||||
(INST VPR:$Rn, VPR:$Rm)>;
|
||||
|
||||
def : NI_Trn2_v4<v4i16, VPR64, TRN2vvv_4h, NI_ei_i32>;
|
||||
def : NI_Trn2_v4<v4i32, VPR128, TRN2vvv_4s, NI_ei_i32>;
|
||||
def : NI_Trn2_v4<v4f32, VPR128, TRN2vvv_4s, NI_ei_f32>;
|
||||
|
||||
// End of implementation for instruction class (Perm)
|
||||
defm : NeonI_Perm_float_pat<"UZP1vvv", Neon_uzp1>;
|
||||
defm : NeonI_Perm_float_pat<"UZP2vvv", Neon_uzp2>;
|
||||
defm : NeonI_Perm_float_pat<"ZIP1vvv", Neon_zip1>;
|
||||
defm : NeonI_Perm_float_pat<"ZIP2vvv", Neon_zip2>;
|
||||
defm : NeonI_Perm_float_pat<"TRN1vvv", Neon_trn1>;
|
||||
defm : NeonI_Perm_float_pat<"TRN2vvv", Neon_trn2>;
|
||||
|
||||
// The followings are for instruction class (3V Diff)
|
||||
|
||||
|
||||
@ -1674,3 +1674,17 @@ entry:
|
||||
%.fca.0.1.insert = insertvalue %struct.poly16x8x2_t %.fca.0.0.insert, <8 x i16> %vtrn1.i, 0, 1
|
||||
ret %struct.poly16x8x2_t %.fca.0.1.insert
|
||||
}
|
||||
|
||||
define %struct.uint8x8x2_t @test_uzp(<16 x i8> %y) {
|
||||
; CHECK: test_uzp:
|
||||
|
||||
%vuzp.i = shufflevector <16 x i8> %y, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
|
||||
%vuzp1.i = shufflevector <16 x i8> %y, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
|
||||
%.fca.0.0.insert = insertvalue %struct.uint8x8x2_t undef, <8 x i8> %vuzp.i, 0, 0
|
||||
%.fca.0.1.insert = insertvalue %struct.uint8x8x2_t %.fca.0.0.insert, <8 x i8> %vuzp1.i, 0, 1
|
||||
ret %struct.uint8x8x2_t %.fca.0.1.insert
|
||||
|
||||
; CHECK: dup {{d[0-9]+}}, {{v[0-9]+}}.d[1]
|
||||
; CHECK-NEXT: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
; CHECK-NEXT: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user