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https://github.com/c64scene-ar/llvm-6502.git
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Add support for generating code for vst{234}lane intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80707 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1484,6 +1484,61 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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N->getOperand(5), N->getOperand(6), Chain };
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return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8);
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}
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case Intrinsic::arm_neon_vst2lane: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vst2lane type");
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case MVT::v8i8: Opc = ARM::VST2LNd8; break;
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case MVT::v4i16: Opc = ARM::VST2LNd16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VST2LNd32; break;
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}
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SDValue Chain = N->getOperand(0);
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
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N->getOperand(3), N->getOperand(4),
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N->getOperand(5), Chain };
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return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7);
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}
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case Intrinsic::arm_neon_vst3lane: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vst3lane type");
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case MVT::v8i8: Opc = ARM::VST3LNd8; break;
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case MVT::v4i16: Opc = ARM::VST3LNd16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VST3LNd32; break;
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}
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SDValue Chain = N->getOperand(0);
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
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N->getOperand(3), N->getOperand(4),
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N->getOperand(5), N->getOperand(6), Chain };
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return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8);
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}
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case Intrinsic::arm_neon_vst4lane: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vst4lane type");
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case MVT::v8i8: Opc = ARM::VST4LNd8; break;
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case MVT::v4i16: Opc = ARM::VST4LNd16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VST4LNd32; break;
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}
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SDValue Chain = N->getOperand(0);
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
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N->getOperand(3), N->getOperand(4),
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N->getOperand(5), N->getOperand(6),
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N->getOperand(7), Chain };
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return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 9);
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}
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}
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}
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}
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@ -1370,6 +1370,26 @@ static SDValue LowerNeonVLDLaneIntrinsic(SDValue Op, SelectionDAG &DAG,
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return DAG.UpdateNodeOperands(Op, &Ops[0], Ops.size());
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}
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static SDValue LowerNeonVSTLaneIntrinsic(SDValue Op, SelectionDAG &DAG,
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unsigned NumVecs) {
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SDNode *Node = Op.getNode();
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EVT VT = Node->getOperand(3).getValueType();
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if (!VT.is64BitVector())
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return SDValue(); // unimplemented
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// Change the lane number operand to be a TargetConstant; otherwise it
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// will be legalized into a register.
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ConstantSDNode *Lane = dyn_cast<ConstantSDNode>(Node->getOperand(NumVecs+3));
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if (!Lane) {
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assert(false && "vst lane number must be a constant");
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return SDValue();
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}
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SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
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Ops[NumVecs+3] = DAG.getTargetConstant(Lane->getZExtValue(), MVT::i32);
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return DAG.UpdateNodeOperands(Op, &Ops[0], Ops.size());
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}
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SDValue
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ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
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unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
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@ -1388,6 +1408,12 @@ ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
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return LowerNeonVSTIntrinsic(Op, DAG, 3);
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case Intrinsic::arm_neon_vst4:
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return LowerNeonVSTIntrinsic(Op, DAG, 4);
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case Intrinsic::arm_neon_vst2lane:
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return LowerNeonVSTLaneIntrinsic(Op, DAG, 2);
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case Intrinsic::arm_neon_vst3lane:
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return LowerNeonVSTLaneIntrinsic(Op, DAG, 3);
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case Intrinsic::arm_neon_vst4lane:
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return LowerNeonVSTLaneIntrinsic(Op, DAG, 4);
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default: return SDValue(); // Don't custom lower most intrinsics.
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}
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}
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@ -300,6 +300,40 @@ class VST4D<string OpcodeStr>
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def VST4d8 : VST4D<"vst4.8">;
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def VST4d16 : VST4D<"vst4.16">;
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def VST4d32 : VST4D<"vst4.32">;
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// VST2LN : Vector Store (single 2-element structure from one lane)
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class VST2LND<string OpcodeStr>
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: NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
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NoItinerary,
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!strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr"),
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"", []>;
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def VST2LNd8 : VST2LND<"vst2.8">;
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def VST2LNd16 : VST2LND<"vst2.16">;
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def VST2LNd32 : VST2LND<"vst2.32">;
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// VST3LN : Vector Store (single 3-element structure from one lane)
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class VST3LND<string OpcodeStr>
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: NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
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nohash_imm:$lane), NoItinerary,
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!strconcat(OpcodeStr,
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"\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), "", []>;
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def VST3LNd8 : VST3LND<"vst3.8">;
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def VST3LNd16 : VST3LND<"vst3.16">;
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def VST3LNd32 : VST3LND<"vst3.32">;
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// VST4LN : Vector Store (single 4-element structure from one lane)
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class VST4LND<string OpcodeStr>
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: NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
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DPR:$src4, nohash_imm:$lane), NoItinerary,
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!strconcat(OpcodeStr,
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"\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"),
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"", []>;
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def VST4LNd8 : VST4LND<"vst4.8">;
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def VST4LNd16 : VST4LND<"vst4.16">;
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def VST4LNd32 : VST4LND<"vst4.32">;
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}
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@ -75,6 +75,9 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd,
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case ARM::VST2d8:
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case ARM::VST2d16:
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case ARM::VST2d32:
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case ARM::VST2LNd8:
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case ARM::VST2LNd16:
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case ARM::VST2LNd32:
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FirstOpnd = 3;
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NumRegs = 2;
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return true;
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@ -82,6 +85,9 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd,
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case ARM::VST3d8:
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case ARM::VST3d16:
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case ARM::VST3d32:
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case ARM::VST3LNd8:
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case ARM::VST3LNd16:
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case ARM::VST3LNd32:
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FirstOpnd = 3;
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NumRegs = 3;
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return true;
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@ -89,6 +95,9 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd,
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case ARM::VST4d8:
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case ARM::VST4d16:
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case ARM::VST4d32:
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case ARM::VST4LNd8:
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case ARM::VST4LNd16:
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case ARM::VST4LNd32:
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FirstOpnd = 3;
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NumRegs = 4;
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return true;
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113
test/CodeGen/ARM/vstlane.ll
Normal file
113
test/CodeGen/ARM/vstlane.ll
Normal file
@ -0,0 +1,113 @@
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; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
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define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK: vst2lanei8:
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;CHECK: vst2.8
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%tmp1 = load <8 x i8>* %B
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call void @llvm.arm.neon.vst2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1)
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ret void
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}
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define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind {
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;CHECK: vst2lanei16:
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;CHECK: vst2.16
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%tmp1 = load <4 x i16>* %B
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call void @llvm.arm.neon.vst2lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
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ret void
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}
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define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind {
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;CHECK: vst2lanei32:
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;CHECK: vst2.32
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%tmp1 = load <2 x i32>* %B
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call void @llvm.arm.neon.vst2lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
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ret void
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}
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define void @vst2lanef(float* %A, <2 x float>* %B) nounwind {
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;CHECK: vst2lanef:
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;CHECK: vst2.32
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%tmp1 = load <2 x float>* %B
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call void @llvm.arm.neon.vst2lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
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ret void
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}
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declare void @llvm.arm.neon.vst2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32) nounwind
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declare void @llvm.arm.neon.vst2lane.v4i16(i8*, <4 x i16>, <4 x i16>, i32) nounwind
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declare void @llvm.arm.neon.vst2lane.v2i32(i8*, <2 x i32>, <2 x i32>, i32) nounwind
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declare void @llvm.arm.neon.vst2lane.v2f32(i8*, <2 x float>, <2 x float>, i32) nounwind
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define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK: vst3lanei8:
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;CHECK: vst3.8
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%tmp1 = load <8 x i8>* %B
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call void @llvm.arm.neon.vst3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1)
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ret void
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}
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define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind {
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;CHECK: vst3lanei16:
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;CHECK: vst3.16
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%tmp1 = load <4 x i16>* %B
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call void @llvm.arm.neon.vst3lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
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ret void
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}
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define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind {
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;CHECK: vst3lanei32:
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;CHECK: vst3.32
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%tmp1 = load <2 x i32>* %B
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call void @llvm.arm.neon.vst3lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
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ret void
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}
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define void @vst3lanef(float* %A, <2 x float>* %B) nounwind {
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;CHECK: vst3lanef:
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;CHECK: vst3.32
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%tmp1 = load <2 x float>* %B
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call void @llvm.arm.neon.vst3lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
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ret void
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}
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declare void @llvm.arm.neon.vst3lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind
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declare void @llvm.arm.neon.vst3lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind
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declare void @llvm.arm.neon.vst3lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
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declare void @llvm.arm.neon.vst3lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32) nounwind
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define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK: vst4lanei8:
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;CHECK: vst4.8
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%tmp1 = load <8 x i8>* %B
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call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1)
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ret void
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}
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define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind {
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;CHECK: vst4lanei16:
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;CHECK: vst4.16
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%tmp1 = load <4 x i16>* %B
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call void @llvm.arm.neon.vst4lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
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ret void
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}
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define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind {
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;CHECK: vst4lanei32:
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;CHECK: vst4.32
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%tmp1 = load <2 x i32>* %B
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call void @llvm.arm.neon.vst4lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
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ret void
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}
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define void @vst4lanef(float* %A, <2 x float>* %B) nounwind {
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;CHECK: vst4lanef:
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;CHECK: vst4.32
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%tmp1 = load <2 x float>* %B
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call void @llvm.arm.neon.vst4lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
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ret void
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}
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declare void @llvm.arm.neon.vst4lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind
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declare void @llvm.arm.neon.vst4lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind
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declare void @llvm.arm.neon.vst4lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
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declare void @llvm.arm.neon.vst4lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32) nounwind
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