From 8a412da0eaf2b694091471a8420e8d47a84816ac Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Mon, 21 Apr 2014 21:45:53 +0000 Subject: [PATCH] Move helper functions earlier in the file. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206798 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp | 107 +++++++++--------- 1 file changed, 53 insertions(+), 54 deletions(-) diff --git a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp index e2740fd07ae..24ed77a020f 100644 --- a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp +++ b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp @@ -1725,6 +1725,56 @@ public: } // end anonymous namespace. +/// isFPR32Register - Check if a register is in the FPR32 register class. +/// (The parser does not have the target register info to check the register +/// class directly.) +static bool isFPR32Register(unsigned Reg) { + using namespace ARM64; + switch (Reg) { + default: + break; + case S0: case S1: case S2: case S3: case S4: case S5: case S6: + case S7: case S8: case S9: case S10: case S11: case S12: case S13: + case S14: case S15: case S16: case S17: case S18: case S19: case S20: + case S21: case S22: case S23: case S24: case S25: case S26: case S27: + case S28: case S29: case S30: case S31: + return true; + } + return false; +} + +/// isGPR32Register - Check if a register is in the GPR32sp register class. +/// (The parser does not have the target register info to check the register +/// class directly.) +static bool isGPR32Register(unsigned Reg) { + using namespace ARM64; + switch (Reg) { + default: + break; + case W0: case W1: case W2: case W3: case W4: case W5: case W6: + case W7: case W8: case W9: case W10: case W11: case W12: case W13: + case W14: case W15: case W16: case W17: case W18: case W19: case W20: + case W21: case W22: case W23: case W24: case W25: case W26: case W27: + case W28: case W29: case W30: case WSP: case WZR: + return true; + } + return false; +} + +static bool isGPR64Register(unsigned Reg) { + using namespace ARM64; + switch (Reg) { + case X0: case X1: case X2: case X3: case X4: case X5: case X6: + case X7: case X8: case X9: case X10: case X11: case X12: case X13: + case X14: case X15: case X16: case X17: case X18: case X19: case X20: + case X21: case X22: case X23: case X24: case X25: case X26: case X27: + case X28: case FP: case LR: case SP: case XZR: + return true; + default: + return false; + } +} + void ARM64Operand::print(raw_ostream &OS) const { switch (Kind) { case k_FPImm: @@ -3310,57 +3360,6 @@ bool ARM64AsmParser::ParseInstruction(ParseInstructionInfo &Info, return false; } -/// isFPR32Register - Check if a register is in the FPR32 register class. -/// (The parser does not have the target register info to check the register -/// class directly.) -static bool isFPR32Register(unsigned Reg) { - using namespace ARM64; - switch (Reg) { - default: - break; - case S0: case S1: case S2: case S3: case S4: case S5: case S6: - case S7: case S8: case S9: case S10: case S11: case S12: case S13: - case S14: case S15: case S16: case S17: case S18: case S19: case S20: - case S21: case S22: case S23: case S24: case S25: case S26: case S27: - case S28: case S29: case S30: case S31: - return true; - } - return false; -} - -/// isGPR32Register - Check if a register is in the GPR32sp register class. -/// (The parser does not have the target register info to check the register -/// class directly.) -static bool isGPR32Register(unsigned Reg) { - using namespace ARM64; - switch (Reg) { - default: - break; - case W0: case W1: case W2: case W3: case W4: case W5: case W6: - case W7: case W8: case W9: case W10: case W11: case W12: case W13: - case W14: case W15: case W16: case W17: case W18: case W19: case W20: - case W21: case W22: case W23: case W24: case W25: case W26: case W27: - case W28: case W29: case W30: case WSP: case WZR: - return true; - } - return false; -} - -static bool isGPR64Reg(unsigned Reg) { - using namespace ARM64; - switch (Reg) { - case X0: case X1: case X2: case X3: case X4: case X5: case X6: - case X7: case X8: case X9: case X10: case X11: case X12: case X13: - case X14: case X15: case X16: case X17: case X18: case X19: case X20: - case X21: case X22: case X23: case X24: case X25: case X26: case X27: - case X28: case FP: case LR: case SP: case XZR: - return true; - default: - return false; - } -} - - // FIXME: This entire function is a giant hack to provide us with decent // operand range validation/diagnostics until TableGen/MC can be extended // to support autogeneration of this kind of validation. @@ -3949,8 +3948,8 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, // reg->reg move. unsigned Reg1 = Op1->getReg(); unsigned Reg2 = Op2->getReg(); - if ((Reg1 == ARM64::SP && isGPR64Reg(Reg2)) || - (Reg2 == ARM64::SP && isGPR64Reg(Reg1)) || + if ((Reg1 == ARM64::SP && isGPR64Register(Reg2)) || + (Reg2 == ARM64::SP && isGPR64Register(Reg1)) || (Reg1 == ARM64::WSP && isGPR32Register(Reg2)) || (Reg2 == ARM64::WSP && isGPR32Register(Reg1))) rewriteMOVRSP(Operands, getContext()); @@ -4179,7 +4178,7 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, else if (NumOperands == 3 && (Tok == "sxtb" || Tok == "uxtb" || Tok == "sxth" || Tok == "uxth")) { ARM64Operand *Op = static_cast(Operands[1]); - if (Op->isReg() && isGPR64Reg(Op->getReg())) { + if (Op->isReg() && isGPR64Register(Op->getReg())) { // The source register can be Wn here, but the matcher expects a // GPR64. Twiddle it here if necessary. ARM64Operand *Op = static_cast(Operands[2]);