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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122559 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -96,6 +96,97 @@ It appears icc use push for parameter passing. Need to investigate.
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//===---------------------------------------------------------------------===//
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//===---------------------------------------------------------------------===//
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This:
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void foo(void);
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void bar(int x, int *P) {
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x >>= 2;
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if (x)
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foo();
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*P = x;
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}
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compiles into:
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movq %rsi, %rbx
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movl %edi, %r14d
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sarl $2, %r14d
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testl %r14d, %r14d
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je LBB0_2
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Instead of doing an explicit test, we can use the flags off the sar. This
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occurs in a bigger testcase like this, which is pretty common:
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#include <vector>
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int test1(std::vector<int> &X) {
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int Sum = 0;
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for (long i = 0, e = X.size(); i != e; ++i)
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X[i] = 0;
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return Sum;
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}
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compiles into:
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movq %rsi, %rbx
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movl %edi, %r14d
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sarl $2, %r14d
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testl %r14d, %r14d
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je LBB0_2
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Instead of doing an explicit test, we can use the flags off the sar. This
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occurs in a bigger testcase like this, which is pretty common:
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#include <vector>
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int test1(std::vector<int> &X) {
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int Sum = 0;
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for (long i = 0, e = X.size(); i != e; ++i)
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X[i] = 0;
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return Sum;
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}
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compiles into:
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movq %rsi, %rbx
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movl %edi, %r14d
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sarl $2, %r14d
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testl %r14d, %r14d
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je LBB0_2
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Instead of doing an explicit test, we can use the flags off the sar. This
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occurs in a bigger testcase like this, which is pretty common:
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#include <vector>
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int test1(std::vector<int> &X) {
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int Sum = 0;
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for (long i = 0, e = X.size(); i != e; ++i)
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X[i] = 0;
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return Sum;
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}
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compiles into:
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movq %rsi, %rbx
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movl %edi, %r14d
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sarl $2, %r14d
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testl %r14d, %r14d
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je LBB0_2
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Instead of doing an explicit test, we can use the flags off the sar. This
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occurs in a bigger testcase like this, which is pretty common in bootstrap:
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#include <vector>
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int test1(std::vector<int> &X) {
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int Sum = 0;
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for (long i = 0, e = X.size(); i != e; ++i)
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X[i] = 0;
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return Sum;
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}
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//===---------------------------------------------------------------------===//
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Only use inc/neg/not instructions on processors where they are faster than
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Only use inc/neg/not instructions on processors where they are faster than
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add/sub/xor. They are slower on the P4 due to only updating some processor
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add/sub/xor. They are slower on the P4 due to only updating some processor
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flags.
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flags.
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