mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Add numeric extend, trunctate to mips fast-isel
Summary: Add numeric extend, trunctate to mips fast-isel Reactivates D4827 Test Plan: fpext.ll loadstoreconv.ll Reviewers: dsanders Subscribers: mcrosier Differential Revision: http://reviews.llvm.org/D5251 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218681 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler
parent
8a23890385
commit
8a6f79e58d
@ -78,6 +78,9 @@ private:
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bool SelectLoad(const Instruction *I);
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bool SelectRet(const Instruction *I);
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bool SelectStore(const Instruction *I);
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bool SelectIntExt(const Instruction *I);
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bool SelectTrunc(const Instruction *I);
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bool SelectFPExt(const Instruction *I);
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bool isTypeLegal(Type *Ty, MVT &VT);
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bool isLoadTypeLegal(Type *Ty, MVT &VT);
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@ -87,6 +90,16 @@ private:
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unsigned MaterializeInt(const Constant *C, MVT VT);
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unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
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bool EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
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bool IsZExt);
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bool EmitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
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bool EmitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
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bool EmitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg);
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bool EmitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg);
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// for some reason, this default is not generated by tablegen
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// so we explicitly generate it here.
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//
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@ -242,6 +255,74 @@ bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
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return true;
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}
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bool MipsFastISel::EmitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg) {
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unsigned ShiftAmt;
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switch (SrcVT.SimpleTy) {
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default:
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return false;
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case MVT::i8:
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ShiftAmt = 24;
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break;
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case MVT::i16:
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ShiftAmt = 16;
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break;
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}
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unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
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EmitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
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EmitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
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return true;
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}
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bool MipsFastISel::EmitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg) {
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switch (SrcVT.SimpleTy) {
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default:
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return false;
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case MVT::i8:
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EmitInst(Mips::SEB, DestReg).addReg(SrcReg);
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break;
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case MVT::i16:
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EmitInst(Mips::SEH, DestReg).addReg(SrcReg);
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break;
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}
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return true;
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}
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bool MipsFastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg, bool IsZExt) {
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if (IsZExt)
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return EmitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
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return EmitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
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}
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bool MipsFastISel::EmitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg) {
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if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
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return false;
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if (Subtarget->hasMips32r2())
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return EmitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
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return EmitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
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}
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bool MipsFastISel::EmitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg) {
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switch (SrcVT.SimpleTy) {
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default:
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return false;
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case MVT::i1:
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EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
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break;
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case MVT::i8:
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EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
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break;
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case MVT::i16:
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EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
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break;
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}
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return true;
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}
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bool MipsFastISel::SelectLoad(const Instruction *I) {
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// Atomic loads need special handling.
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if (cast<LoadInst>(I)->isAtomic())
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@ -304,6 +385,79 @@ bool MipsFastISel::SelectRet(const Instruction *I) {
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return true;
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}
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// Attempt to fast-select a floating-point extend instruction.
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bool MipsFastISel::SelectFPExt(const Instruction *I) {
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Value *Src = I->getOperand(0);
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EVT SrcVT = TLI.getValueType(Src->getType(), true);
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EVT DestVT = TLI.getValueType(I->getType(), true);
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if (SrcVT != MVT::f32 || DestVT != MVT::f64)
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return false;
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unsigned SrcReg =
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getRegForValue(Src); // his must be a 32 bit floating point register class
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// maybe we should handle this differently
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if (!SrcReg)
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return false;
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unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
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EmitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
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updateValueMap(I, DestReg);
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return true;
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}
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bool MipsFastISel::SelectIntExt(const Instruction *I) {
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Type *DestTy = I->getType();
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Value *Src = I->getOperand(0);
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Type *SrcTy = Src->getType();
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bool isZExt = isa<ZExtInst>(I);
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unsigned SrcReg = getRegForValue(Src);
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if (!SrcReg)
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return false;
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EVT SrcEVT, DestEVT;
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SrcEVT = TLI.getValueType(SrcTy, true);
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DestEVT = TLI.getValueType(DestTy, true);
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if (!SrcEVT.isSimple())
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return false;
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if (!DestEVT.isSimple())
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return false;
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MVT SrcVT = SrcEVT.getSimpleVT();
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MVT DestVT = DestEVT.getSimpleVT();
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unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
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if (!EmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
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return false;
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updateValueMap(I, ResultReg);
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return true;
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}
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bool MipsFastISel::SelectTrunc(const Instruction *I) {
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// The high bits for a type smaller than the register size are assumed to be
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// undefined.
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Value *Op = I->getOperand(0);
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EVT SrcVT, DestVT;
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SrcVT = TLI.getValueType(Op->getType(), true);
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DestVT = TLI.getValueType(I->getType(), true);
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if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
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return false;
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if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
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return false;
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unsigned SrcReg = getRegForValue(Op);
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if (!SrcReg)
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return false;
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// Because the high bits are undefined, a truncate doesn't generate
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// any code.
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updateValueMap(I, SrcReg);
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return true;
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}
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bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
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if (!TargetSupported)
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return false;
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@ -316,10 +470,16 @@ bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
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return SelectStore(I);
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case Instruction::Ret:
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return SelectRet(I);
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case Instruction::Trunc:
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return SelectTrunc(I);
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case Instruction::ZExt:
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case Instruction::SExt:
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return SelectIntExt(I);
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case Instruction::FPExt:
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return SelectFPExt(I);
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}
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return false;
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}
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}
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unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
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int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
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@ -352,13 +512,15 @@ unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) {
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// TLS not supported at this time.
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if (IsThreadLocal)
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return 0;
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EmitInst(Mips::LW, DestReg).addReg(MFI->getGlobalBaseReg()).addGlobalAddress(
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GV, 0, MipsII::MO_GOT);
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EmitInst(Mips::LW, DestReg)
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.addReg(MFI->getGlobalBaseReg())
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.addGlobalAddress(GV, 0, MipsII::MO_GOT);
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if ((GV->hasInternalLinkage() ||
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(GV->hasLocalLinkage() && !isa<Function>(GV)))) {
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unsigned TempReg = createResultReg(RC);
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EmitInst(Mips::ADDiu, TempReg).addReg(DestReg).addGlobalAddress(
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GV, 0, MipsII::MO_ABS_LO);
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EmitInst(Mips::ADDiu, TempReg)
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.addReg(DestReg)
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.addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
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DestReg = TempReg;
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}
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return DestReg;
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@ -401,6 +563,7 @@ unsigned MipsFastISel::Materialize32BitInt(int64_t Imm,
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}
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return ResultReg;
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}
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}
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namespace llvm {
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FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
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21
test/CodeGen/Mips/Fast-ISel/fpext.ll
Normal file
21
test/CodeGen/Mips/Fast-ISel/fpext.ll
Normal file
@ -0,0 +1,21 @@
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
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; RUN: < %s | FileCheck %s
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@f = global float 0x40147E6B80000000, align 4
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@d_f = common global double 0.000000e+00, align 8
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@.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1
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; Function Attrs: nounwind
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define void @dv() #0 {
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entry:
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%0 = load float* @f, align 4
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%conv = fpext float %0 to double
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; CHECK: cvt.d.s $f{{[0-9]+}}, $f{{[0-9]+}}
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store double %conv, double* @d_f, align 8
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ret void
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}
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attributes #1 = { nounwind }
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179
test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll
Normal file
179
test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll
Normal file
@ -0,0 +1,179 @@
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
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; RUN: < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s -check-prefix=mips32r2
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
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; RUN: < %s | FileCheck %s -check-prefix=mips32
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@b2 = global i8 0, align 1
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@b1 = global i8 1, align 1
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@uc1 = global i8 0, align 1
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@uc2 = global i8 -1, align 1
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@sc1 = global i8 -128, align 1
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@sc2 = global i8 127, align 1
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@ss1 = global i16 -32768, align 2
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@ss2 = global i16 32767, align 2
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@us1 = global i16 0, align 2
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@us2 = global i16 -1, align 2
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@ssi = global i16 0, align 2
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@ssj = global i16 0, align 2
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@i = global i32 0, align 4
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@j = global i32 0, align 4
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@.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1
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@.str1 = private unnamed_addr constant [7 x i8] c"%i %i\0A\00", align 1
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; Function Attrs: nounwind
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define void @_Z3b_iv() {
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entry:
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; CHECK-LABEL: .ent _Z3b_iv
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%0 = load i8* @b1, align 1
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%tobool = trunc i8 %0 to i1
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%frombool = zext i1 %tobool to i8
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store i8 %frombool, i8* @b2, align 1
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%1 = load i8* @b2, align 1
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%tobool1 = trunc i8 %1 to i1
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%conv = zext i1 %tobool1 to i32
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store i32 %conv, i32* @i, align 4
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; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; CHECK: andi $[[REG2:[0-9]+]], $[[REG1]], 1
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; CHECK: sb $[[REG2]], 0(${{[0-9]+}})
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ret void
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; CHECK: .end _Z3b_iv
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}
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; Function Attrs: nounwind
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define void @_Z4uc_iv() {
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entry:
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; CHECK-LABEL: .ent _Z4uc_iv
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%0 = load i8* @uc1, align 1
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%conv = zext i8 %0 to i32
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store i32 %conv, i32* @i, align 4
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%1 = load i8* @uc2, align 1
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%conv1 = zext i8 %1 to i32
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; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255
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store i32 %conv1, i32* @j, align 4
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ret void
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; CHECK: .end _Z4uc_iv
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}
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; Function Attrs: nounwind
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define void @_Z4sc_iv() {
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entry:
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; mips32r2-LABEL: .ent _Z4sc_iv
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; mips32-LABEL: .ent _Z4sc_iv
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%0 = load i8* @sc1, align 1
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%conv = sext i8 %0 to i32
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store i32 %conv, i32* @i, align 4
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%1 = load i8* @sc2, align 1
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%conv1 = sext i8 %1 to i32
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store i32 %conv1, i32* @j, align 4
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; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; mips32r2: seb ${{[0-9]+}}, $[[REG1]]
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; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24
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; mips32: sra ${{[0-9]+}}, $[[REG2]], 24
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ret void
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; CHECK: .end _Z4sc_iv
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}
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; Function Attrs: nounwind
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define void @_Z4us_iv() {
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entry:
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; CHECK-LABEL: .ent _Z4us_iv
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%0 = load i16* @us1, align 2
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%conv = zext i16 %0 to i32
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store i32 %conv, i32* @i, align 4
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%1 = load i16* @us2, align 2
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%conv1 = zext i16 %1 to i32
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store i32 %conv1, i32* @j, align 4
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ret void
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; CHECK: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; CHECK: andi ${{[0-9]+}}, $[[REG1]], 65535
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; CHECK: .end _Z4us_iv
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}
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; Function Attrs: nounwind
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define void @_Z4ss_iv() {
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entry:
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; mips32r2-LABEL: .ent _Z4ss_iv
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; mips32=LABEL: .ent _Z4ss_iv
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%0 = load i16* @ss1, align 2
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%conv = sext i16 %0 to i32
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store i32 %conv, i32* @i, align 4
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%1 = load i16* @ss2, align 2
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%conv1 = sext i16 %1 to i32
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store i32 %conv1, i32* @j, align 4
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; mips32r2: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; mips32r2: seh ${{[0-9]+}}, $[[REG1]]
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; mips32: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 16
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; mips32: sra ${{[0-9]+}}, $[[REG2]], 16
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ret void
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; CHECK: .end _Z4ss_iv
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}
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; Function Attrs: nounwind
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define void @_Z4b_ssv() {
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entry:
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; CHECK-LABEL: .ent _Z4b_ssv
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%0 = load i8* @b2, align 1
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%tobool = trunc i8 %0 to i1
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%conv = zext i1 %tobool to i16
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store i16 %conv, i16* @ssi, align 2
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ret void
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; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
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; CHECK: .end _Z4b_ssv
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}
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; Function Attrs: nounwind
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define void @_Z5uc_ssv() {
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entry:
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; CHECK-LABEL: .ent _Z5uc_ssv
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%0 = load i8* @uc1, align 1
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%conv = zext i8 %0 to i16
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store i16 %conv, i16* @ssi, align 2
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%1 = load i8* @uc2, align 1
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%conv1 = zext i8 %1 to i16
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; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255
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|
||||
store i16 %conv1, i16* @ssj, align 2
|
||||
ret void
|
||||
; CHECK: .end _Z5uc_ssv
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @_Z5sc_ssv() {
|
||||
entry:
|
||||
; mips32r2-LABEL: .ent _Z5sc_ssv
|
||||
; mips32-LABEL: .ent _Z5sc_ssv
|
||||
%0 = load i8* @sc1, align 1
|
||||
%conv = sext i8 %0 to i16
|
||||
store i16 %conv, i16* @ssi, align 2
|
||||
%1 = load i8* @sc2, align 1
|
||||
%conv1 = sext i8 %1 to i16
|
||||
store i16 %conv1, i16* @ssj, align 2
|
||||
; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
|
||||
; mips32r2: seb ${{[0-9]+}}, $[[REG1]]
|
||||
; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
|
||||
; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24
|
||||
; mips32: sra ${{[0-9]+}}, $[[REG2]], 24
|
||||
|
||||
ret void
|
||||
; CHECK: .end _Z5sc_ssv
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user