6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-03-04 21:31:03 +00:00
Code Issues Projects Releases Wiki Activity

R600/SI: Fixup CopyToReg register class in PostprocessISelDAG()

Browse Source 
The CopyToReg nodes will sometimes try to copy a value from a VGPR to an
SGPR.  This kind of copy is not possible, so we need to detect
VGPR->SGPR copies and do something else.  The current strategy is to
replace these copies with VGPR->VGPR copies and hope that all the users
of CopyToReg can accept VGPRs as arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183132 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2013-06-03 17:39:46 +00:00
parent 132183510f
commit 8a72c73032
1 changed files with 33 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
lib/Target/R600/AMDILISelDAGToDAG.cpp
View File

@ -18,6 +18,7 @@
#include "R600InstrInfo.h"
#include "SIISelLowering.h"
#include "llvm/ADT/ValueMap.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
@ -649,18 +650,45 @@ bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
if (Subtarget.device()->getGeneration() < AMDGPUDeviceInfo::HD7XXX) {
return;
}
// Go over all selected nodes and try to fold them a bit more
const AMDGPUTargetLowering& Lowering = ((const AMDGPUTargetLowering&)TLI);
for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
E = CurDAG->allnodes_end(); I != E; ++I) {
MachineSDNode *Node = dyn_cast<MachineSDNode>(I);
if (!Node)
SDNode *Node = I;
switch (Node->getOpcode()) {
// Fix the register class in copy to CopyToReg nodes - ISel will always
// use SReg classes for 64-bit copies, but this is not always what we want.
case ISD::CopyToReg: {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
SDValue Val = Node->getOperand(2);
const TargetRegisterClass *RC = RegInfo->getRegClass(Reg);
if (RC != &AMDGPU::SReg_64RegClass) {
continue;
}
if (!Val.getNode()->isMachineOpcode()) {
continue;
}
const MCInstrDesc Desc = TM.getInstrInfo()->get(Val.getNode()->getMachineOpcode());
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
RegInfo->setRegClass(Reg, TRI->getRegClass(Desc.OpInfo[0].RegClass));
continue;
}
}
MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
if (!MachineNode)
continue;
SDNode *ResNode = Lowering.PostISelFolding(Node, *CurDAG);
if (ResNode != Node)
SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
if (ResNode != Node) {
ReplaceUses(Node, ResNode);
}
}
}