6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-24 08:24:33 +00:00
Code Issues Projects Releases Wiki Activity

Create Thumb2 versions of STC/LDC, and reenable the relevant tests.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2011-09-07 21:10:42 +00:00
parent ed1cb6defa
commit 8a83f71301
3 changed files with 134 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -997,6 +997,22 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
case ARM::STCL_PRE:
case ARM::STCL_POST:
case ARM::STCL_OPTION:
case ARM::t2LDC_OFFSET:
case ARM::t2LDC_PRE:
case ARM::t2LDC_POST:
case ARM::t2LDC_OPTION:
case ARM::t2LDCL_OFFSET:
case ARM::t2LDCL_PRE:
case ARM::t2LDCL_POST:
case ARM::t2LDCL_OPTION:
case ARM::t2STC_OFFSET:
case ARM::t2STC_PRE:
case ARM::t2STC_POST:
case ARM::t2STC_OPTION:
case ARM::t2STCL_OFFSET:
case ARM::t2STCL_PRE:
case ARM::t2STCL_POST:
case ARM::t2STCL_OPTION:
if (coproc == 0xA || coproc == 0xB)
return MCDisassembler::Fail;
break;
@ -1021,6 +1037,12 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
case ARM::STCL_POST:
case ARM::LDC2L_POST:
case ARM::STC2L_POST:
case ARM::t2LDC_OPTION:
case ARM::t2LDCL_OPTION:
case ARM::t2STC_OPTION:
case ARM::t2STCL_OPTION:
case ARM::t2LDCL_POST:
case ARM::t2STCL_POST:
break;
default:
Inst.addOperand(MCOperand::CreateReg(0));
@ -1040,6 +1062,8 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
switch (Inst.getOpcode()) {
case ARM::LDCL_POST:
case ARM::STCL_POST:
case ARM::t2LDCL_POST:
case ARM::t2STCL_POST:
case ARM::LDC2L_POST:
case ARM::STC2L_POST:
imm |= U << 8;
@ -1051,6 +1075,10 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
case ARM::STCL_OPTION:
case ARM::STC2_OPTION:
case ARM::STC2L_OPTION:
case ARM::t2LDC_OPTION:
case ARM::t2LDCL_OPTION:
case ARM::t2STC_OPTION:
case ARM::t2STCL_OPTION:
Inst.addOperand(MCOperand::CreateImm(imm));
break;
default: