6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-22 13:29:44 +00:00
Code Issues Projects Releases Wiki Activity

Oops, remove these too.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21272 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-04-13 02:47:57 +00:00
parent 519f40ba4e
commit 8a8dbfa57c
1 changed files with 2 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -943,10 +943,8 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
case ISD::SHL: case ISD::SHL:
case ISD::SRL: case ISD::SRL:
case ISD::SRA: case ISD::SRA:
if (N2.getOpcode() == ISD::ZERO_EXTEND_INREG || if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG)
N2.getOpcode() == ISD::SIGN_EXTEND_INREG) {
return getNode(Opcode, VT, N1, N2.getOperand(0)); return getNode(Opcode, VT, N1, N2.getOperand(0));
}
break; break;
} }
@ -1042,10 +1040,8 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
case ISD::SRA_PARTS: case ISD::SRA_PARTS:
case ISD::SRL_PARTS: case ISD::SRL_PARTS:
case ISD::SHL_PARTS: case ISD::SHL_PARTS:
if (N3.getOpcode() == ISD::ZERO_EXTEND_INREG || if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG)
N3.getOpcode() == ISD::SIGN_EXTEND_INREG) {
return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); return getNode(Opcode, VT, N1, N2, N3.getOperand(0));
}
break; break;
} }