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Add new shorter predicates for testing machine operands for various types:

Browse Source 
e.g. MO.isMBB() instead of MO.isMachineBasicBlock().  I don't plan on 
switching everything over, so new clients should just start using the 
shorter names.

Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(), 
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45464 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-12-30 23:10:15 +00:00
parent 78d34664e7
commit 8aa797aa51
40 changed files with 185 additions and 192 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
include/llvm/CodeGen/MachineOperand.h
View File

@ -122,6 +122,15 @@ public:
bool isGlobalAddress() const { return OpKind == MO_GlobalAddress; }
bool isExternalSymbol() const { return OpKind == MO_ExternalSymbol; }
bool isReg() const { return OpKind == MO_Register; }
bool isImm() const { return OpKind == MO_Immediate; }
bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
bool isFI() const { return OpKind == MO_FrameIndex; }
bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
bool isJTI() const { return OpKind == MO_JumpTableIndex; }
bool isGlobal() const { return OpKind == MO_GlobalAddress; }
bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
//===--------------------------------------------------------------------===//
// Accessors for Register Operands
//===--------------------------------------------------------------------===//
@ -215,10 +224,6 @@ public:
assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
return Contents.MBB;
}
MachineBasicBlock *getMachineBasicBlock() const {
assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
return Contents.MBB;
}
int getIndex() const {
assert((isFrameIndex() || isConstantPoolIndex() || isJumpTableIndex()) &&
@ -226,19 +231,17 @@ public:
return Contents.OffsetedInfo.Val.Index;
}
int getFrameIndex() const { return getIndex(); }
unsigned getConstantPoolIndex() const { return getIndex(); }
unsigned getJumpTableIndex() const { return getIndex(); }
GlobalValue *getGlobal() const {
assert(isGlobalAddress() && "Wrong MachineOperand accessor");
return Contents.OffsetedInfo.Val.GV;
}
int getOffset() const {
assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex()) &&
"Wrong MachineOperand accessor");
return Contents.OffsetedInfo.Offset;
}
const char *getSymbolName() const {
assert(isExternalSymbol() && "Wrong MachineOperand accessor");
return Contents.OffsetedInfo.Val.SymbolName;
@ -265,10 +268,7 @@ public:
Contents.OffsetedInfo.Val.Index = Idx;
}
void setConstantPoolIndex(unsigned Idx) { setIndex(Idx); }
void setJumpTableIndex(unsigned Idx) { setIndex(Idx); }
void setMachineBasicBlock(MachineBasicBlock *MBB) {
void setMBB(MachineBasicBlock *MBB) {
assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
Contents.MBB = MBB;
}
@ -327,7 +327,7 @@ public:
}
static MachineOperand CreateMBB(MachineBasicBlock *MBB) {
MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
Op.setMachineBasicBlock(MBB);
Op.setMBB(MBB);
return Op;
}
static MachineOperand CreateFI(unsigned Idx) {

2
lib/CodeGen/AsmPrinter.cpp
View File

@ -1226,7 +1226,7 @@ void AsmPrinter::printInlineAsm(const MachineInstr *MI) const {
++OpNo; // Skip over the ID number.
if (Modifier[0]=='l') // labels are target independent
printBasicBlockLabel(MI->getOperand(OpNo).getMachineBasicBlock(),
printBasicBlockLabel(MI->getOperand(OpNo).getMBB(),
false, false);
else {
AsmPrinter *AP = const_cast<AsmPrinter*>(this);

12
lib/CodeGen/BranchFolding.cpp
View File

@ -172,8 +172,8 @@ bool BranchFolder::runOnMachineFunction(MachineFunction &MF) {
for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
MachineOperand &Op = I->getOperand(op);
if (!Op.isJumpTableIndex()) continue;
unsigned NewIdx = JTMapping[Op.getJumpTableIndex()];
Op.setJumpTableIndex(NewIdx);
unsigned NewIdx = JTMapping[Op.getIndex()];
Op.setIndex(NewIdx);
// Remember that this JT is live.
JTIsLive[NewIdx] = true;
@ -210,14 +210,12 @@ static unsigned HashMachineInstr(const MachineInstr *MI) {
case MachineOperand::MO_Register: OperandHash = Op.getReg(); break;
case MachineOperand::MO_Immediate: OperandHash = Op.getImm(); break;
case MachineOperand::MO_MachineBasicBlock:
OperandHash = Op.getMachineBasicBlock()->getNumber();
OperandHash = Op.getMBB()->getNumber();
break;
case MachineOperand::MO_FrameIndex: OperandHash = Op.getFrameIndex(); break;
case MachineOperand::MO_FrameIndex:
case MachineOperand::MO_ConstantPoolIndex:
OperandHash = Op.getConstantPoolIndex();
break;
case MachineOperand::MO_JumpTableIndex:
OperandHash = Op.getJumpTableIndex();
OperandHash = Op.getIndex();
break;
case MachineOperand::MO_GlobalAddress:
case MachineOperand::MO_ExternalSymbol:

2
lib/CodeGen/LiveVariables.cpp
View File

@ -696,6 +696,6 @@ void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
PHIVarInfo[BBI->getOperand(i + 1).getMachineBasicBlock()->getNumber()].
PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()].
push_back(BBI->getOperand(i).getReg());
}

5
lib/CodeGen/MachineBasicBlock.cpp
View File

@ -214,9 +214,8 @@ void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old,
// Scan the operands of this machine instruction, replacing any uses of Old
// with New.
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
if (I->getOperand(i).isMachineBasicBlock() &&
I->getOperand(i).getMachineBasicBlock() == Old)
I->getOperand(i).setMachineBasicBlock(New);
if (I->getOperand(i).isMBB() && I->getOperand(i).getMBB() == Old)
I->getOperand(i).setMBB(New);
}
// Update the successor information. If New was already a successor, just

17
lib/CodeGen/MachineInstr.cpp
View File

@ -40,12 +40,11 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
case MachineOperand::MO_MachineBasicBlock:
return getMBB() == Other.getMBB();
case MachineOperand::MO_FrameIndex:
return getFrameIndex() == Other.getFrameIndex();
return getIndex() == Other.getIndex();
case MachineOperand::MO_ConstantPoolIndex:
return getConstantPoolIndex() == Other.getConstantPoolIndex() &&
getOffset() == Other.getOffset();
return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
case MachineOperand::MO_JumpTableIndex:
return getJumpTableIndex() == Other.getJumpTableIndex();
return getIndex() == Other.getIndex();
case MachineOperand::MO_GlobalAddress:
return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
case MachineOperand::MO_ExternalSymbol:
@ -100,19 +99,19 @@ void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
break;
case MachineOperand::MO_MachineBasicBlock:
OS << "mbb<"
<< ((Value*)getMachineBasicBlock()->getBasicBlock())->getName()
<< "," << (void*)getMachineBasicBlock() << ">";
<< ((Value*)getMBB()->getBasicBlock())->getName()
<< "," << (void*)getMBB() << ">";
break;
case MachineOperand::MO_FrameIndex:
OS << "<fi#" << getFrameIndex() << ">";
OS << "<fi#" << getIndex() << ">";
break;
case MachineOperand::MO_ConstantPoolIndex:
OS << "<cp#" << getConstantPoolIndex();
OS << "<cp#" << getIndex();
if (getOffset()) OS << "+" << getOffset();
OS << ">";
break;
case MachineOperand::MO_JumpTableIndex:
OS << "<jt#" << getJumpTableIndex() << ">";
OS << "<jt#" << getIndex() << ">";
break;
case MachineOperand::MO_GlobalAddress:
OS << "<ga:" << ((Value*)getGlobal())->getName();

12
lib/CodeGen/PHIElimination.cpp
View File

@ -174,9 +174,8 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
// Adjust the VRegPHIUseCount map to account for the removal of this PHI
// node.
for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
--VRegPHIUseCount[BBVRegPair(
MPhi->getOperand(i + 1).getMachineBasicBlock(),
MPhi->getOperand(i).getReg())];
--VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i + 1).getMBB(),
MPhi->getOperand(i).getReg())];
// Now loop over all of the incoming arguments, changing them to copy into
// the IncomingReg register in the corresponding predecessor basic block.
@ -189,7 +188,7 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
// Get the MachineBasicBlock equivalent of the BasicBlock that is the
// source path the PHI.
MachineBasicBlock &opBlock = *MPhi->getOperand(i).getMachineBasicBlock();
MachineBasicBlock &opBlock = *MPhi->getOperand(i).getMBB();
// Check to make sure we haven't already emitted the copy for this block.
// This can happen because PHI nodes may have multiple entries for the
@ -339,7 +338,6 @@ void PNE::analyzePHINodes(const MachineFunction& Fn) {
for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
++VRegPHIUseCount[BBVRegPair(
BBI->getOperand(i + 1).getMachineBasicBlock(),
BBI->getOperand(i).getReg())];
++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i + 1).getMBB(),
BBI->getOperand(i).getReg())];
}

2
lib/CodeGen/StrongPHIElimination.cpp
View File

@ -385,7 +385,7 @@ void StrongPHIElimination::processBlock(MachineBasicBlock* MBB) {
UnionedBlocks.count(SrcInfo.DefInst->getParent())) {
// add a copy from a_i to p in Waiting[From[a_i]]
MachineBasicBlock* From = P->getOperand(i).getMachineBasicBlock();
MachineBasicBlock* From = P->getOperand(i).getMBB();
Waiting[From].insert(std::make_pair(SrcReg, DestReg));
UsedByAnother.insert(SrcReg);
} else {

10
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -275,7 +275,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
break;
}
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMachineBasicBlock());
printBasicBlockLabel(MO.getMBB());
return;
case MachineOperand::MO_GlobalAddress: {
bool isCallOp = Modifier && !strcmp(Modifier, "call");
@ -319,11 +319,11 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
}
case MachineOperand::MO_ConstantPoolIndex:
O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
<< '_' << MO.getConstantPoolIndex();
<< '_' << MO.getIndex();
break;
case MachineOperand::MO_JumpTableIndex:
O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
<< '_' << MO.getJumpTableIndex();
<< '_' << MO.getIndex();
break;
default:
O << "<unknown operand type>"; abort (); break;
@ -655,7 +655,7 @@ void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNo,
<< '_' << ID << ":\n";
} else {
assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
unsigned CPI = MI->getOperand(OpNo).getConstantPoolIndex();
unsigned CPI = MI->getOperand(OpNo).getIndex();
const MachineConstantPoolEntry &MCPE = // Chasing pointers is fun?
MI->getParent()->getParent()->getConstantPool()->getConstants()[CPI];
@ -675,7 +675,7 @@ void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNo,
void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNo) {
const MachineOperand &MO1 = MI->getOperand(OpNo);
const MachineOperand &MO2 = MI->getOperand(OpNo+1); // Unique Id
unsigned JTI = MO1.getJumpTableIndex();
unsigned JTI = MO1.getIndex();
O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
<< '_' << JTI << '_' << MO2.getImm() << ":\n";

6
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -143,11 +143,11 @@ int Emitter::getMachineOpValue(const MachineInstr &MI, unsigned OpIndex) {
} else if (MO.isExternalSymbol()) {
emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
} else if (MO.isConstantPoolIndex()) {
emitConstPoolAddress(MO.getConstantPoolIndex(), ARM::reloc_arm_relative);
emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_relative);
} else if (MO.isJumpTableIndex()) {
emitJumpTableAddress(MO.getJumpTableIndex(), ARM::reloc_arm_relative);
emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
} else if (MO.isMachineBasicBlock()) {
emitMachineBasicBlock(MO.getMachineBasicBlock());
emitMachineBasicBlock(MO.getMBB());
}
return rv;

22
lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -467,7 +467,7 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &Fn,
}
// Remember that this is a user of a CP entry.
unsigned CPI = I->getOperand(op).getConstantPoolIndex();
unsigned CPI = I->getOperand(op).getIndex();
MachineInstr *CPEMI = CPEMIs[CPI];
unsigned MaxOffs = ((1 << Bits)-1) * Scale;
CPUsers.push_back(CPUser(I, CPEMI, MaxOffs));
@ -802,7 +802,7 @@ int ARMConstantIslands::LookForExistingCPEntry(CPUser& U, unsigned UserOffset)
}
// No. Look for previously created clones of the CPE that are in range.
unsigned CPI = CPEMI->getOperand(1).getConstantPoolIndex();
unsigned CPI = CPEMI->getOperand(1).getIndex();
std::vector<CPEntry> &CPEs = CPEntries[CPI];
for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
// We already tried this one
@ -818,7 +818,7 @@ int ARMConstantIslands::LookForExistingCPEntry(CPUser& U, unsigned UserOffset)
// Change the CPI in the instruction operand to refer to the clone.
for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
if (UserMI->getOperand(j).isConstantPoolIndex()) {
UserMI->getOperand(j).setConstantPoolIndex(CPEs[i].CPI);
UserMI->getOperand(j).setIndex(CPEs[i].CPI);
break;
}
// Adjust the refcount of the clone...
@ -998,7 +998,7 @@ bool ARMConstantIslands::HandleConstantPoolUser(MachineFunction &Fn,
CPUser &U = CPUsers[CPUserIndex];
MachineInstr *UserMI = U.MI;
MachineInstr *CPEMI = U.CPEMI;
unsigned CPI = CPEMI->getOperand(1).getConstantPoolIndex();
unsigned CPI = CPEMI->getOperand(1).getIndex();
unsigned Size = CPEMI->getOperand(2).getImm();
MachineBasicBlock *NewMBB;
// Compute this only once, it's expensive. The 4 or 8 is the value the
@ -1057,8 +1057,8 @@ bool ARMConstantIslands::HandleConstantPoolUser(MachineFunction &Fn,
// Finally, change the CPI in the instruction operand to be ID.
for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
if (UserMI->getOperand(i).isConstantPoolIndex()) {
UserMI->getOperand(i).setConstantPoolIndex(ID);
if (UserMI->getOperand(i).isCPI()) {
UserMI->getOperand(i).setIndex(ID);
break;
}
@ -1139,7 +1139,7 @@ bool ARMConstantIslands::BBIsInRange(MachineInstr *MI,MachineBasicBlock *DestBB,
/// away to fit in its displacement field.
bool ARMConstantIslands::FixUpImmediateBr(MachineFunction &Fn, ImmBranch &Br) {
MachineInstr *MI = Br.MI;
MachineBasicBlock *DestBB = MI->getOperand(0).getMachineBasicBlock();
MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
// Check to see if the DestBB is already in-range.
if (BBIsInRange(MI, DestBB, Br.MaxDisp))
@ -1179,7 +1179,7 @@ ARMConstantIslands::FixUpUnconditionalBr(MachineFunction &Fn, ImmBranch &Br) {
bool
ARMConstantIslands::FixUpConditionalBr(MachineFunction &Fn, ImmBranch &Br) {
MachineInstr *MI = Br.MI;
MachineBasicBlock *DestBB = MI->getOperand(0).getMachineBasicBlock();
MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
// Add a unconditional branch to the destination and invert the branch
// condition to jump over it:
@ -1210,11 +1210,11 @@ ARMConstantIslands::FixUpConditionalBr(MachineFunction &Fn, ImmBranch &Br) {
// =>
// bne L2
// b L1
MachineBasicBlock *NewDest = BMI->getOperand(0).getMachineBasicBlock();
MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
if (BBIsInRange(MI, NewDest, Br.MaxDisp)) {
DOUT << " Invert Bcc condition and swap its destination with " << *BMI;
BMI->getOperand(0).setMachineBasicBlock(DestBB);
MI->getOperand(0).setMachineBasicBlock(NewDest);
BMI->getOperand(0).setMBB(DestBB);
MI->getOperand(0).setMBB(NewDest);
MI->getOperand(1).setImm(CC);
return true;
}

24
lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -71,7 +71,7 @@ unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) co
MI->getOperand(3).isImmediate() &&
MI->getOperand(2).getReg() == 0 &&
MI->getOperand(3).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
break;
@ -80,7 +80,7 @@ unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) co
if (MI->getOperand(1).isFrameIndex() &&
MI->getOperand(2).isImmediate() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
break;
@ -88,7 +88,7 @@ unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) co
if (MI->getOperand(1).isFrameIndex() &&
MI->getOperand(2).isImmediate() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
break;
@ -105,7 +105,7 @@ unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) con
MI->getOperand(3).isImmediate() &&
MI->getOperand(2).getReg() == 0 &&
MI->getOperand(3).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
break;
@ -114,7 +114,7 @@ unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) con
if (MI->getOperand(1).isFrameIndex() &&
MI->getOperand(2).isImmediate() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
break;
@ -122,7 +122,7 @@ unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) con
if (MI->getOperand(1).isFrameIndex() &&
MI->getOperand(2).isImmediate() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
break;
@ -319,12 +319,12 @@ bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
unsigned LastOpc = LastInst->getOpcode();
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
if (LastOpc == ARM::B || LastOpc == ARM::tB) {
TBB = LastInst->getOperand(0).getMachineBasicBlock();
TBB = LastInst->getOperand(0).getMBB();
return false;
}
if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
// Block ends with fall-through condbranch.
TBB = LastInst->getOperand(0).getMachineBasicBlock();
TBB = LastInst->getOperand(0).getMBB();
Cond.push_back(LastInst->getOperand(1));
Cond.push_back(LastInst->getOperand(2));
return false;
@ -343,10 +343,10 @@ bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
unsigned SecondLastOpc = SecondLastInst->getOpcode();
if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
(SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
TBB = SecondLastInst->getOperand(0).getMBB();
Cond.push_back(SecondLastInst->getOperand(1));
Cond.push_back(SecondLastInst->getOperand(2));
FBB = LastInst->getOperand(0).getMachineBasicBlock();
FBB = LastInst->getOperand(0).getMBB();
return false;
}
@ -354,7 +354,7 @@ bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
// one is not executed, so remove it.
if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
(LastOpc == ARM::B || LastOpc == ARM::tB)) {
TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
TBB = SecondLastInst->getOperand(0).getMBB();
I = LastInst;
I->eraseFromParent();
return false;
@ -576,7 +576,7 @@ unsigned ARM::GetInstSize(MachineInstr *MI) {
unsigned NumOps = TID->numOperands;
MachineOperand JTOP =
MI->getOperand(NumOps - ((TID->Flags & M_PREDICABLE) ? 3 : 2));
unsigned JTI = JTOP.getJumpTableIndex();
unsigned JTI = JTOP.getIndex();
MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
assert(JTI < JT.size());

4
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -148,7 +148,7 @@ static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
else if (MO.isImmediate())
MIB = MIB.addImm(MO.getImm());
else if (MO.isFrameIndex())
MIB = MIB.addFrameIndex(MO.getFrameIndex());
MIB = MIB.addFrameIndex(MO.getIndex());
else
assert(0 && "Unknown operand for ARMInstrAddOperand!");
@ -870,7 +870,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
}
unsigned FrameReg = ARM::SP;
int FrameIndex = MI.getOperand(i).getFrameIndex();
int FrameIndex = MI.getOperand(i).getIndex();
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
MF.getFrameInfo()->getStackSize() + SPAdj;

6
lib/Target/Alpha/AlphaAsmPrinter.cpp
View File

@ -100,12 +100,12 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
return;
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMachineBasicBlock());
printBasicBlockLabel(MO.getMBB());
return;
case MachineOperand::MO_ConstantPoolIndex:
O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
<< MO.getConstantPoolIndex();
<< MO.getIndex();
return;
case MachineOperand::MO_ExternalSymbol:
@ -122,7 +122,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
case MachineOperand::MO_JumpTableIndex:
O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
<< '_' << MO.getJumpTableIndex();
<< '_' << MO.getIndex();
return;
default:

8
lib/Target/Alpha/AlphaCodeEmitter.cpp
View File

@ -202,13 +202,11 @@ int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
Reloc, MO.getSymbolName(),
Offset, true));
else
MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
Reloc, MO.getConstantPoolIndex(),
Offset));
MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
Reloc, MO.getIndex(), Offset));
} else if (MO.isMachineBasicBlock()) {
MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
Alpha::reloc_bsr,
MO.getMachineBasicBlock()));
Alpha::reloc_bsr, MO.getMBB()));
}else {
cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
abort();

14
lib/Target/Alpha/AlphaInstrInfo.cpp
View File

@ -58,7 +58,7 @@ AlphaInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
case Alpha::LDS:
case Alpha::LDT:
if (MI->getOperand(1).isFrameIndex()) {
FrameIndex = MI->getOperand(1).getFrameIndex();
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
break;
@ -76,7 +76,7 @@ AlphaInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
case Alpha::STS:
case Alpha::STT:
if (MI->getOperand(1).isFrameIndex()) {
FrameIndex = MI->getOperand(1).getFrameIndex();
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
break;
@ -168,12 +168,12 @@ bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TB
// If there is only one terminator instruction, process it.
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
if (LastInst->getOpcode() == Alpha::BR) {
TBB = LastInst->getOperand(0).getMachineBasicBlock();
TBB = LastInst->getOperand(0).getMBB();
return false;
} else if (LastInst->getOpcode() == Alpha::COND_BRANCH_I ||
LastInst->getOpcode() == Alpha::COND_BRANCH_F) {
// Block ends with fall-through condbranch.
TBB = LastInst->getOperand(2).getMachineBasicBlock();
TBB = LastInst->getOperand(2).getMBB();
Cond.push_back(LastInst->getOperand(0));
Cond.push_back(LastInst->getOperand(1));
return false;
@ -194,10 +194,10 @@ bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TB
if ((SecondLastInst->getOpcode() == Alpha::COND_BRANCH_I ||
SecondLastInst->getOpcode() == Alpha::COND_BRANCH_F) &&
LastInst->getOpcode() == Alpha::BR) {
TBB = SecondLastInst->getOperand(2).getMachineBasicBlock();
TBB = SecondLastInst->getOperand(2).getMBB();
Cond.push_back(SecondLastInst->getOperand(0));
Cond.push_back(SecondLastInst->getOperand(1));
FBB = LastInst->getOperand(0).getMachineBasicBlock();
FBB = LastInst->getOperand(0).getMBB();
return false;
}
@ -205,7 +205,7 @@ bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TB
// executed, so remove it.
if (SecondLastInst->getOpcode() == Alpha::BR &&
LastInst->getOpcode() == Alpha::BR) {
TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
TBB = SecondLastInst->getOperand(0).getMBB();
I = LastInst;
I->eraseFromParent();
return false;

2
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -329,7 +329,7 @@ void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
}
int FrameIndex = MI.getOperand(i).getFrameIndex();
int FrameIndex = MI.getOperand(i).getIndex();
// Add the base register of R30 (SP) or R15 (FP).
MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);

6
lib/Target/CellSPU/SPUAsmPrinter.cpp
View File

@ -304,16 +304,16 @@ void SPUAsmPrinter::printOp(const MachineOperand &MO) {
return;
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMachineBasicBlock());
printBasicBlockLabel(MO.getMBB());
return;
case MachineOperand::MO_JumpTableIndex:
O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
<< '_' << MO.getJumpTableIndex();
<< '_' << MO.getIndex();
// FIXME: PIC relocation model
return;
case MachineOperand::MO_ConstantPoolIndex:
O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
<< '_' << MO.getConstantPoolIndex();
<< '_' << MO.getIndex();
return;
case MachineOperand::MO_ExternalSymbol:
// Computing the address of an external symbol, not calling it.

4
lib/Target/CellSPU/SPUInstrInfo.cpp
View File

@ -139,7 +139,7 @@ SPUInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
case SPU::LQXr16:
if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getFrameIndex();
FrameIndex = MI->getOperand(2).getIndex();
return MI->getOperand(0).getReg();
}
break;
@ -173,7 +173,7 @@ SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
// case SPU::STQXr8:
if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getFrameIndex();
FrameIndex = MI->getOperand(2).getIndex();
return MI->getOperand(0).getReg();
}
break;

6
lib/Target/CellSPU/SPURegisterInfo.cpp
View File

@ -267,7 +267,7 @@ void SPURegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
else if (MO.isImmediate())
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
MIB.addFrameIndex(MO.getIndex());
}
NewMIs.push_back(MIB);
}
@ -353,7 +353,7 @@ void SPURegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
else if (MO.isImmediate())
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
MIB.addFrameIndex(MO.getIndex());
}
NewMIs.push_back(MIB);
}
@ -598,7 +598,7 @@ SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
}
MachineOperand &SPOp = MI.getOperand(i);
int FrameIndex = SPOp.getFrameIndex();
int FrameIndex = SPOp.getIndex();
// Now add the frame object offset to the offset from r1.
int Offset = MFI->getObjectOffset(FrameIndex);

5
lib/Target/IA64/IA64AsmPrinter.cpp
View File

@ -175,12 +175,11 @@ void IA64AsmPrinter::printOp(const MachineOperand &MO,
O << MO.getImm();
return;
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMachineBasicBlock());
printBasicBlockLabel(MO.getMBB());
return;
case MachineOperand::MO_ConstantPoolIndex: {
O << "@gprel(" << TAI->getPrivateGlobalPrefix()
<< "CPI" << getFunctionNumber() << "_"
<< MO.getConstantPoolIndex() << ")";
<< "CPI" << getFunctionNumber() << "_" << MO.getIndex() << ")";
return;
}

6
lib/Target/IA64/IA64RegisterInfo.cpp
View File

@ -86,7 +86,7 @@ void IA64RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
else if (MO.isImmediate())
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
MIB.addFrameIndex(MO.getIndex());
}
MIB.addReg(SrcReg, false, false, isKill);
NewMIs.push_back(MIB);
@ -138,7 +138,7 @@ void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
else if (MO.isImmediate())
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
MIB.addFrameIndex(MO.getIndex());
}
NewMIs.push_back(MIB);
return;
@ -262,7 +262,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
}
int FrameIndex = MI.getOperand(i).getFrameIndex();
int FrameIndex = MI.getOperand(i).getIndex();
// choose a base register: ( hasFP? framepointer : stack pointer )
unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;

6
lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -380,7 +380,7 @@ printOperand(const MachineInstr *MI, int opNum)
break;
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMachineBasicBlock());
printBasicBlockLabel(MO.getMBB());
return;
case MachineOperand::MO_GlobalAddress:
@ -393,13 +393,13 @@ printOperand(const MachineInstr *MI, int opNum)
case MachineOperand::MO_JumpTableIndex:
O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
<< '_' << MO.getJumpTableIndex();
<< '_' << MO.getIndex();
break;
// FIXME: Verify correct
case MachineOperand::MO_ConstantPoolIndex:
O << TAI->getPrivateGlobalPrefix() << "CPI"
<< getFunctionNumber() << "_" << MO.getConstantPoolIndex();
<< getFunctionNumber() << "_" << MO.getIndex();
break;
default:

14
lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -74,7 +74,7 @@ isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const
(MI->getOperand(1).isImmediate()) && // the imm is zero
(isZeroImm(MI->getOperand(1))))
{
FrameIndex = MI->getOperand(2).getFrameIndex();
FrameIndex = MI->getOperand(2).getIndex();
return MI->getOperand(0).getReg();
}
}
@ -95,7 +95,7 @@ isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const
(MI->getOperand(1).isImmediate()) && // the imm is zero
(isZeroImm(MI->getOperand(1))))
{
FrameIndex = MI->getOperand(0).getFrameIndex();
FrameIndex = MI->getOperand(0).getIndex();
return MI->getOperand(2).getReg();
}
}
@ -180,7 +180,7 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
// Unconditional branch
if (LastOpc == Mips::J) {
TBB = LastInst->getOperand(0).getMachineBasicBlock();
TBB = LastInst->getOperand(0).getMBB();
return false;
}
@ -193,7 +193,7 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
if (LastOpc != Mips::COND_INVALID) {
int LastNumOp = LastInst->getNumOperands();
TBB = LastInst->getOperand(LastNumOp-1).getMachineBasicBlock();
TBB = LastInst->getOperand(LastNumOp-1).getMBB();
Cond.push_back(MachineOperand::CreateImm(BranchCode));
for (int i=0; i<LastNumOp-1; i++) {
@ -218,21 +218,21 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
if (SecondLastOpc != Mips::COND_INVALID && LastOpc == Mips::J) {
int SecondNumOp = SecondLastInst->getNumOperands();
TBB = SecondLastInst->getOperand(SecondNumOp-1).getMachineBasicBlock();
TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
Cond.push_back(MachineOperand::CreateImm(BranchCode));
for (int i=0; i<SecondNumOp-1; i++) {
Cond.push_back(SecondLastInst->getOperand(i));
}
FBB = LastInst->getOperand(0).getMachineBasicBlock();
FBB = LastInst->getOperand(0).getMBB();
return false;
}
// If the block ends with two unconditional branches, handle it. The last
// one is not executed, so remove it.
if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
TBB = SecondLastInst->getOperand(0).getMBB();
I = LastInst;
I->eraseFromParent();
return false;

6
lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -111,7 +111,7 @@ void MipsRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
else if (MO.isImmediate())
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
MIB.addFrameIndex(MO.getIndex());
}
NewMIs.push_back(MIB);
return;
@ -142,7 +142,7 @@ void MipsRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
else if (MO.isImmediate())
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
MIB.addFrameIndex(MO.getIndex());
}
NewMIs.push_back(MIB);
return;
@ -339,7 +339,7 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
"Instr doesn't have FrameIndex operand!");
}
int FrameIndex = MI.getOperand(i).getFrameIndex();
int FrameIndex = MI.getOperand(i).getIndex();
int stackSize = MF.getFrameInfo()->getStackSize();
int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);

6
lib/Target/PowerPC/PPCAsmPrinter.cpp
View File

@ -360,16 +360,16 @@ void PPCAsmPrinter::printOp(const MachineOperand &MO) {
return;
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMachineBasicBlock());
printBasicBlockLabel(MO.getMBB());
return;
case MachineOperand::MO_JumpTableIndex:
O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
<< '_' << MO.getJumpTableIndex();
<< '_' << MO.getIndex();
// FIXME: PIC relocation model
return;
case MachineOperand::MO_ConstantPoolIndex:
O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
<< '_' << MO.getConstantPoolIndex();
<< '_' << MO.getIndex();
return;
case MachineOperand::MO_ExternalSymbol:
// Computing the address of an external symbol, not calling it.

2
lib/Target/PowerPC/PPCBranchSelector.cpp
View File

@ -136,7 +136,7 @@ bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
// Determine the offset from the current branch to the destination
// block.
MachineBasicBlock *Dest = I->getOperand(2).getMachineBasicBlock();
MachineBasicBlock *Dest = I->getOperand(2).getMBB();
int BranchSize;
if (Dest->getNumber() <= MBB.getNumber()) {

7
lib/Target/PowerPC/PPCCodeEmitter.cpp
View File

@ -195,11 +195,11 @@ int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
Reloc, MO.getSymbolName(), 0);
} else if (MO.isConstantPoolIndex()) {
R = MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
Reloc, MO.getConstantPoolIndex(), 0);
Reloc, MO.getIndex(), 0);
} else {
assert(MO.isJumpTableIndex());
R = MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
Reloc, MO.getJumpTableIndex(), 0);
Reloc, MO.getIndex(), 0);
}
// If in PIC mode, we need to encode the negated address of the
@ -223,8 +223,7 @@ int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
else // BCC instruction
Reloc = PPC::reloc_pcrel_bcx;
MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
Reloc,
MO.getMachineBasicBlock()));
Reloc, MO.getMBB()));
} else {
cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
abort();

22
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -99,9 +99,9 @@ unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
case PPC::LWZ:
case PPC::LFS:
case PPC::LFD:
if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getFrameIndex();
if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFI()) {
FrameIndex = MI->getOperand(2).getIndex();
return MI->getOperand(0).getReg();
}
break;
@ -117,9 +117,9 @@ unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
case PPC::STW:
case PPC::STFS:
case PPC::STFD:
if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getFrameIndex();
if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFI()) {
FrameIndex = MI->getOperand(2).getIndex();
return MI->getOperand(0).getReg();
}
break;
@ -184,11 +184,11 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
// If there is only one terminator instruction, process it.
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
if (LastInst->getOpcode() == PPC::B) {
TBB = LastInst->getOperand(0).getMachineBasicBlock();
TBB = LastInst->getOperand(0).getMBB();
return false;
} else if (LastInst->getOpcode() == PPC::BCC) {
// Block ends with fall-through condbranch.
TBB = LastInst->getOperand(2).getMachineBasicBlock();
TBB = LastInst->getOperand(2).getMBB();
Cond.push_back(LastInst->getOperand(0));
Cond.push_back(LastInst->getOperand(1));
return false;
@ -208,10 +208,10 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
// If the block ends with PPC::B and PPC:BCC, handle it.
if (SecondLastInst->getOpcode() == PPC::BCC &&
LastInst->getOpcode() == PPC::B) {
TBB = SecondLastInst->getOperand(2).getMachineBasicBlock();
TBB = SecondLastInst->getOperand(2).getMBB();
Cond.push_back(SecondLastInst->getOperand(0));
Cond.push_back(SecondLastInst->getOperand(1));
FBB = LastInst->getOperand(0).getMachineBasicBlock();
FBB = LastInst->getOperand(0).getMBB();
return false;
}
@ -219,7 +219,7 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
// executed, so remove it.
if (SecondLastInst->getOpcode() == PPC::B &&
LastInst->getOpcode() == PPC::B) {
TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
TBB = SecondLastInst->getOperand(0).getMBB();
I = LastInst;
I->eraseFromParent();
return false;

13
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -187,8 +187,7 @@ void PPCRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
if (Addr[0].isFrameIndex()) {
StoreRegToStackSlot(TII, SrcReg, isKill, Addr[0].getFrameIndex(), RC,
NewMIs);
StoreRegToStackSlot(TII, SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs);
return;
}
@ -216,7 +215,7 @@ void PPCRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
else if (MO.isImmediate())
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
MIB.addFrameIndex(MO.getIndex());
}
NewMIs.push_back(MIB);
return;
@ -295,9 +294,9 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
void PPCRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
SmallVectorImpl<MachineInstr*> &NewMIs) const{
if (Addr[0].isFrameIndex()) {
LoadRegFromStackSlot(TII, DestReg, Addr[0].getFrameIndex(), RC, NewMIs);
LoadRegFromStackSlot(TII, DestReg, Addr[0].getIndex(), RC, NewMIs);
return;
}
@ -326,7 +325,7 @@ void PPCRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
else if (MO.isImmediate())
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
MIB.addFrameIndex(MO.getIndex());
}
NewMIs.push_back(MIB);
return;
@ -766,7 +765,7 @@ void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
OffsetOperandNo = FIOperandNo-1;
// Get the frame index.
int FrameIndex = MI.getOperand(FIOperandNo).getFrameIndex();
int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
// Get the frame pointer save index. Users of this index are primarily
// DYNALLOC instructions.

4
lib/Target/Sparc/SparcAsmPrinter.cpp
View File

@ -155,7 +155,7 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
O << (int)MO.getImm();
break;
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMachineBasicBlock());
printBasicBlockLabel(MO.getMBB());
return;
case MachineOperand::MO_GlobalAddress:
O << Mang->getValueName(MO.getGlobal());
@ -165,7 +165,7 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
break;
case MachineOperand::MO_ConstantPoolIndex:
O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
<< MO.getConstantPoolIndex();
<< MO.getIndex();
break;
default:
O << "<unknown operand type>"; abort (); break;

4
lib/Target/Sparc/SparcInstrInfo.cpp
View File

@ -72,7 +72,7 @@ unsigned SparcInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
MI->getOpcode() == SP::LDDFri) {
if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
}
@ -91,7 +91,7 @@ unsigned SparcInstrInfo::isStoreToStackSlot(MachineInstr *MI,
MI->getOpcode() == SP::STDFri) {
if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
MI->getOperand(1).getImm() == 0) {
FrameIndex = MI->getOperand(0).getFrameIndex();
FrameIndex = MI->getOperand(0).getIndex();
return MI->getOperand(2).getReg();
}
}

18
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -69,8 +69,10 @@ void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
else {
assert(MO.isFI());
MIB.addFrameIndex(MO.getIndex());
}
}
MIB.addReg(SrcReg, false, false, isKill);
NewMIs.push_back(MIB);
@ -107,12 +109,14 @@ void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isRegister())
if (MO.isReg())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
else if (MO.isImm())
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
else {
assert(MO.isFI());
MIB.addFrameIndex(MO.getIndex());
}
}
NewMIs.push_back(MIB);
return;
@ -241,7 +245,7 @@ void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
}
int FrameIndex = MI.getOperand(i).getFrameIndex();
int FrameIndex = MI.getOperand(i).getIndex();
// Addressable stack objects are accessed using neg. offsets from %fp
MachineFunction &MF = *MI.getParent()->getParent();

8
lib/Target/TargetInstrInfo.cpp
View File

@ -62,14 +62,14 @@ bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister()) {
if (MO.isReg()) {
MO.setReg(Pred[j].getReg());
MadeChange = true;
} else if (MO.isImmediate()) {
} else if (MO.isImm()) {
MO.setImm(Pred[j].getImm());
MadeChange = true;
} else if (MO.isMachineBasicBlock()) {
MO.setMachineBasicBlock(Pred[j].getMachineBasicBlock());
} else if (MO.isMBB()) {
MO.setMBB(Pred[j].getMBB());
MadeChange = true;
}
++j;

6
lib/Target/X86/X86ATTAsmPrinter.cpp
View File

@ -232,13 +232,13 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
O << MO.getImm();
return;
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMachineBasicBlock());
printBasicBlockLabel(MO.getMBB());
return;
case MachineOperand::MO_JumpTableIndex: {
bool isMemOp = Modifier && !strcmp(Modifier, "mem");
if (!isMemOp) O << '$';
O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << "_"
<< MO.getJumpTableIndex();
<< MO.getIndex();
if (TM.getRelocationModel() == Reloc::PIC_) {
if (Subtarget->isPICStyleStub())
@ -256,7 +256,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
bool isMemOp = Modifier && !strcmp(Modifier, "mem");
if (!isMemOp) O << '$';
O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
<< MO.getConstantPoolIndex();
<< MO.getIndex();
if (TM.getRelocationModel() == Reloc::PIC_) {
if (Subtarget->isPICStyleStub())

22
lib/Target/X86/X86CodeEmitter.cpp
View File

@ -247,11 +247,11 @@ void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
PCAdj, false, IsPIC);
} else if (RelocOp->isConstantPoolIndex()) {
// Must be in 64-bit mode.
emitConstPoolAddress(RelocOp->getConstantPoolIndex(), X86::reloc_pcrel_word,
emitConstPoolAddress(RelocOp->getIndex(), X86::reloc_pcrel_word,
RelocOp->getOffset(), PCAdj, IsPIC);
} else if (RelocOp->isJumpTableIndex()) {
// Must be in 64-bit mode.
emitJumpTableAddress(RelocOp->getJumpTableIndex(), X86::reloc_pcrel_word,
emitJumpTableAddress(RelocOp->getIndex(), X86::reloc_pcrel_word,
PCAdj, IsPIC);
} else {
assert(0 && "Unknown value to relocate!");
@ -272,14 +272,14 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI,
if (Is64BitMode) {
DispForReloc = &Op3;
} else {
DispVal += MCE.getConstantPoolEntryAddress(Op3.getConstantPoolIndex());
DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
DispVal += Op3.getOffset();
}
} else if (Op3.isJumpTableIndex()) {
if (Is64BitMode) {
DispForReloc = &Op3;
} else {
DispVal += MCE.getJumpTableEntryAddress(Op3.getJumpTableIndex());
DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
}
} else {
DispVal = Op3.getImm();
@ -601,7 +601,7 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
if (CurOp != NumOps) {
const MachineOperand &MO = MI.getOperand(CurOp++);
if (MO.isMachineBasicBlock()) {
emitPCRelativeBlockAddress(MO.getMachineBasicBlock());
emitPCRelativeBlockAddress(MO.getMBB());
} else if (MO.isGlobalAddress()) {
bool NeedStub = Is64BitMode ||
Opcode == X86::TAILJMPd ||
@ -642,9 +642,9 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
else if (MO1.isExternalSymbol())
emitExternalSymbolAddress(MO1.getSymbolName(), rt, IsPIC);
else if (MO1.isConstantPoolIndex())
emitConstPoolAddress(MO1.getConstantPoolIndex(), rt, IsPIC);
emitConstPoolAddress(MO1.getIndex(), rt, IsPIC);
else if (MO1.isJumpTableIndex())
emitJumpTableAddress(MO1.getJumpTableIndex(), rt, IsPIC);
emitJumpTableAddress(MO1.getIndex(), rt, IsPIC);
}
}
break;
@ -711,9 +711,9 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
else if (MO1.isExternalSymbol())
emitExternalSymbolAddress(MO1.getSymbolName(), rt, IsPIC);
else if (MO1.isConstantPoolIndex())
emitConstPoolAddress(MO1.getConstantPoolIndex(), rt, IsPIC);
emitConstPoolAddress(MO1.getIndex(), rt, IsPIC);
else if (MO1.isJumpTableIndex())
emitJumpTableAddress(MO1.getJumpTableIndex(), rt, IsPIC);
emitJumpTableAddress(MO1.getIndex(), rt, IsPIC);
}
}
break;
@ -745,9 +745,9 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
else if (MO.isExternalSymbol())
emitExternalSymbolAddress(MO.getSymbolName(), rt, IsPIC);
else if (MO.isConstantPoolIndex())
emitConstPoolAddress(MO.getConstantPoolIndex(), rt, IsPIC);
emitConstPoolAddress(MO.getIndex(), rt, IsPIC);
else if (MO.isJumpTableIndex())
emitJumpTableAddress(MO.getJumpTableIndex(), rt, IsPIC);
emitJumpTableAddress(MO.getIndex(), rt, IsPIC);
}
}
break;

2
lib/Target/X86/X86ISelLowering.cpp
View File

@ -5838,7 +5838,7 @@ X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
AM.Base.Reg = Op.getReg();
} else {
AM.BaseType = X86AddressMode::FrameIndexBase;
AM.Base.FrameIndex = Op.getFrameIndex();
AM.Base.FrameIndex = Op.getIndex();
}
Op = MI->getOperand(1);
if (Op.isImmediate())

22
lib/Target/X86/X86InstrInfo.cpp
View File

@ -71,12 +71,12 @@ unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
case X86::MOVAPDrm:
case X86::MMX_MOVD64rm:
case X86::MMX_MOVQ64rm:
if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
MI->getOperand(2).getImm() == 1 &&
MI->getOperand(3).getReg() == 0 &&
MI->getOperand(4).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
break;
@ -102,12 +102,12 @@ unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
case X86::MMX_MOVD64mr:
case X86::MMX_MOVQ64mr:
case X86::MMX_MOVNTQmr:
if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
MI->getOperand(1).getImm() == 1 &&
MI->getOperand(2).getReg() == 0 &&
MI->getOperand(3).getImm() == 0) {
FrameIndex = MI->getOperand(0).getFrameIndex();
FrameIndex = MI->getOperand(0).getIndex();
return MI->getOperand(4).getReg();
}
break;
@ -689,7 +689,7 @@ bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
// it's an unconditional, conditional, or indirect branch.
if (LastInst->getOpcode() == X86::JMP) {
TBB = LastInst->getOperand(0).getMachineBasicBlock();
TBB = LastInst->getOperand(0).getMBB();
return false;
}
X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
@ -697,7 +697,7 @@ bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
return true; // Can't handle indirect branch.
// Otherwise, block ends with fall-through condbranch.
TBB = LastInst->getOperand(0).getMachineBasicBlock();
TBB = LastInst->getOperand(0).getMBB();
Cond.push_back(MachineOperand::CreateImm(BranchCode));
return false;
}
@ -713,9 +713,9 @@ bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
// If the block ends with X86::JMP and a conditional branch, handle it.
X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode());
if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) {
TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
TBB = SecondLastInst->getOperand(0).getMBB();
Cond.push_back(MachineOperand::CreateImm(BranchCode));
FBB = LastInst->getOperand(0).getMachineBasicBlock();
FBB = LastInst->getOperand(0).getMBB();
return false;
}
@ -723,7 +723,7 @@ bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
// executed, so remove it.
if (SecondLastInst->getOpcode() == X86::JMP &&
LastInst->getOpcode() == X86::JMP) {
TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
TBB = SecondLastInst->getOperand(0).getMBB();
I = LastInst;
I->eraseFromParent();
return false;

6
lib/Target/X86/X86IntelAsmPrinter.cpp
View File

@ -135,20 +135,20 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
O << MO.getImm();
return;
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMachineBasicBlock());
printBasicBlockLabel(MO.getMBB());
return;
case MachineOperand::MO_JumpTableIndex: {
bool isMemOp = Modifier && !strcmp(Modifier, "mem");
if (!isMemOp) O << "OFFSET ";
O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
<< "_" << MO.getJumpTableIndex();
<< "_" << MO.getIndex();
return;
}
case MachineOperand::MO_ConstantPoolIndex: {
bool isMemOp = Modifier && !strcmp(Modifier, "mem");
if (!isMemOp) O << "OFFSET ";
O << "[" << TAI->getPrivateGlobalPrefix() << "CPI"
<< getFunctionNumber() << "_" << MO.getConstantPoolIndex();
<< getFunctionNumber() << "_" << MO.getIndex();
int Offset = MO.getOffset();
if (Offset > 0)
O << " + " << Offset;

8
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -781,13 +781,13 @@ static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
else if (MO.isImmediate())
MIB = MIB.addImm(MO.getImm());
else if (MO.isFrameIndex())
MIB = MIB.addFrameIndex(MO.getFrameIndex());
MIB = MIB.addFrameIndex(MO.getIndex());
else if (MO.isGlobalAddress())
MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
else if (MO.isConstantPoolIndex())
MIB = MIB.addConstantPoolIndex(MO.getConstantPoolIndex(), MO.getOffset());
MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset());
else if (MO.isJumpTableIndex())
MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
MIB = MIB.addJumpTableIndex(MO.getIndex());
else if (MO.isExternalSymbol())
MIB = MIB.addExternalSymbol(MO.getSymbolName());
else
@ -1611,7 +1611,7 @@ void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
}
int FrameIndex = MI.getOperand(i).getFrameIndex();
int FrameIndex = MI.getOperand(i).getIndex();
// This must be part of a four operand memory reference. Replace the
// FrameIndex with base register with EBP. Add an offset to the offset.
MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);