6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-21 21:29:41 +00:00
Code Issues Projects Releases Wiki Activity

[mips] Refactor sign-extension-in-register instructions.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170940 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-12-21 22:41:52 +00:00
parent 7de001b97e
commit 8aaed99a99
3 changed files with 21 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -192,8 +192,8 @@ def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>;
def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>;
/// Sign Ext In Register Instructions.
def SEB64 : SignExtInReg<0x10, "seb", i8, CPU64Regs>;
def SEH64 : SignExtInReg<0x18, "seh", i16, CPU64Regs>;
def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10>;
def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18>;
/// Count Leading
def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>;

14
lib/Target/Mips/MipsInstrFormats.td
View File

@ -326,6 +326,20 @@ class MTLO_FM<bits<6> funct> {
let Inst{5-0} = funct;
}
class SEB_FM<bits<5> funct> {
bits<5> rd;
bits<5> rt;
bits<32> Inst;
let Inst{31-26} = 0x1f;
let Inst{25-21} = 0;
let Inst{20-16} = rt;
let Inst{15-11} = rd;
let Inst{10-6} = funct;
let Inst{5-0} = 0x20;
}
//===----------------------------------------------------------------------===//
//
// FLOATING POINT INSTRUCTION FORMATS

14
lib/Target/Mips/MipsInstrInfo.td
View File

@ -703,13 +703,9 @@ class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
}
// Sign Extend in Register.
class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt,
RegisterClass RC>:
FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt),
!strconcat(instr_asm, "\t$rd, $rt"),
[(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> {
let rs = 0;
let shamt = sa;
class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> :
InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"),
[(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> {
let Predicates = [HasSEInReg, HasStdEnc];
}
@ -966,8 +962,8 @@ def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>;
def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>;
/// Sign Ext In Register Instructions.
def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>;
def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>;
def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10>;
def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18>;
/// Count Leading
def CLZ : CountLeading0<0x20, "clz", CPURegs>;