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Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141854 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2011-10-13 07:09:14 +00:00
parent d501c714cd
commit 8ab1d1e900
7 changed files with 105 additions and 5 deletions
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7
lib/Target/X86/X86.td
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@ -104,6 +104,8 @@ def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
"Support 16-bit floating point conversion instructions">;
def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
"Support LZCNT instruction">;
def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
"Support BMI instructions">;
//===----------------------------------------------------------------------===//
// X86 processors supported.
@ -157,6 +159,11 @@ def : Proc<"corei7-avx", [FeatureSSE42, FeatureCMPXCHG16B,
def : Proc<"core-avx-i", [FeatureSSE42, FeatureCMPXCHG16B,
FeatureAES, FeatureCLMUL,
FeatureRDRAND, FeatureF16C]>;
// Haswell
def : Proc<"core-avx2", [FeatureSSE42, FeatureCMPXCHG16B, FeatureAES,
FeatureCLMUL, FeatureRDRAND, FeatureF16C,
FeatureFMA3, FeatureMOVBE, FeatureLZCNT,
FeatureBMI]>;
def : Proc<"k6", [FeatureMMX]>;
def : Proc<"k6-2", [Feature3DNow]>;

14
lib/Target/X86/X86ISelLowering.cpp
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@ -379,11 +379,15 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::FREM , MVT::f80 , Expand);
setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
if (Subtarget->is64Bit())
setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
if (Subtarget->hasBMI()) {
setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
} else {
setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
if (Subtarget->is64Bit())
setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
}
if (Subtarget->hasLZCNT()) {
setOperationAction(ISD::CTLZ , MVT::i8 , Promote);

32
lib/Target/X86/X86InstrInfo.td
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@ -478,6 +478,7 @@ def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
def HasF16C : Predicate<"Subtarget->hasF16C()">;
def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
def HasBMI : Predicate<"Subtarget->hasBMI()">;
def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
@ -1372,6 +1373,37 @@ let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
(implicit EFLAGS)]>, XS;
}
//===----------------------------------------------------------------------===//
// BMI Instructions
//
let Predicates = [HasBMI], Defs = [EFLAGS] in {
def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
"tzcnt{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
OpSize;
def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
"tzcnt{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (cttz (loadi16 addr:$src))),
(implicit EFLAGS)]>, XS, OpSize;
def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
"tzcnt{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
"tzcnt{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (cttz (loadi32 addr:$src))),
(implicit EFLAGS)]>, XS;
def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
"tzcnt{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
XS;
def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"tzcnt{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (cttz (loadi64 addr:$src))),
(implicit EFLAGS)]>, XS;
}
//===----------------------------------------------------------------------===//
// Subsystems.
//===----------------------------------------------------------------------===//

4
lib/Target/X86/X86Subtarget.h
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@ -102,6 +102,9 @@ protected:
/// HasLZCNT - Processor has LZCNT instruction.
bool HasLZCNT;
/// HasBMI - Processor has BMI1 instructions.
bool HasBMI;
/// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
bool IsBTMemSlow;
@ -188,6 +191,7 @@ public:
bool hasRDRAND() const { return HasRDRAND; }
bool hasF16C() const { return HasF16C; }
bool hasLZCNT() const { return HasLZCNT; }
bool hasBMI() const { return HasBMI; }
bool isBTMemSlow() const { return IsBTMemSlow; }
bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
bool hasVectorUAMem() const { return HasVectorUAMem; }

38
test/CodeGen/X86/bmi.ll Normal file
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@ -0,0 +1,38 @@
; RUN: llc < %s -march=x86-64 -mattr=+bmi | FileCheck %s
define i32 @t1(i32 %x) nounwind {
%tmp = tail call i32 @llvm.cttz.i32( i32 %x )
ret i32 %tmp
; CHECK: t1:
; CHECK: tzcntl
}
declare i32 @llvm.cttz.i32(i32) nounwind readnone
define i16 @t2(i16 %x) nounwind {
%tmp = tail call i16 @llvm.cttz.i16( i16 %x )
ret i16 %tmp
; CHECK: t2:
; CHECK: tzcntw
}
declare i16 @llvm.cttz.i16(i16) nounwind readnone
define i64 @t3(i64 %x) nounwind {
%tmp = tail call i64 @llvm.cttz.i64( i64 %x )
ret i64 %tmp
; CHECK: t3:
; CHECK: tzcntq
}
declare i64 @llvm.cttz.i64(i64) nounwind readnone
define i8 @t4(i8 %x) nounwind {
%tmp = tail call i8 @llvm.cttz.i8( i8 %x )
ret i8 %tmp
; CHECK: t4:
; CHECK: tzcntw
}
declare i8 @llvm.cttz.i8(i8) nounwind readnone

9
test/MC/Disassembler/X86/simple-tests.txt
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@ -497,3 +497,12 @@
# CHECK: lzcntq %rax, %rax
0xf3 0x48 0x0f 0xbd 0xc0
# CHECK: tzcntl %eax, %eax
0xf3 0x0f 0xbc 0xc0
# CHECK: tzcntw %ax, %ax
0x66 0xf3 0x0f 0xbc 0xc0
# CHECK: tzcntq %rax, %rax
0xf3 0x48 0x0f 0xbc 0xc0

6
test/MC/Disassembler/X86/x86-32.txt
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@ -477,3 +477,9 @@
# CHECK: lzcntw %ax, %ax
0x66 0xf3 0x0f 0xbd 0xc0
# CHECK: tzcntl %eax, %eax
0xf3 0x0f 0xbc 0xc0
# CHECK: tzcntw %ax, %ax
0x66 0xf3 0x0f 0xbc 0xc0