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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-12 07:37:34 +00:00
Add and commonize encoder support for all immediates.
Stub out some dummy fixups to make things work.
We can now emit fixups like this:
subl $20, %esp ## encoding: [0x83,0xec,A]
## fixup A - offset: 2, value: 20, kind: fixup_1byte_imm
Emitting $20 as a single-byte fixup to be later resolved
by the assembler is ridiculous of course (vs just emitting
the byte) but this is a failure of the matcher, which
should be producing an imm of 20, not an MCExpr of 20.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95860 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
a38c707d82
commit
8b0f7a7d86
@ -23,11 +23,11 @@ using namespace llvm;
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namespace llvm {
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namespace X86 {
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enum Fixups {
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reloc_pcrel_word = FirstTargetFixupKind,
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reloc_picrel_word,
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reloc_absolute_word,
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reloc_absolute_word_sext,
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reloc_absolute_dword
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// FIXME: This is just a stub.
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fixup_1byte_imm = FirstTargetFixupKind,
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fixup_2byte_imm,
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fixup_4byte_imm,
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fixup_8byte_imm
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};
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}
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}
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@ -48,16 +48,15 @@ public:
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~X86MCCodeEmitter() {}
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unsigned getNumFixupKinds() const {
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return 5;
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return 4;
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}
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MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
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static MCFixupKindInfo Infos[] = {
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{ "reloc_pcrel_word", 0, 4 * 8 },
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{ "reloc_picrel_word", 0, 4 * 8 },
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{ "reloc_absolute_word", 0, 4 * 8 },
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{ "reloc_absolute_word_sext", 0, 4 * 8 },
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{ "reloc_absolute_dword", 0, 8 * 8 }
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{ "fixup_1byte_imm", 0, 1 * 8 },
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{ "fixup_2byte_imm", 0, 2 * 8 },
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{ "fixup_4byte_imm", 0, 4 * 8 },
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{ "fixup_8byte_imm", 0, 8 * 8 }
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};
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assert(Kind >= FirstTargetFixupKind && Kind < MaxTargetFixupKind &&
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@ -146,16 +145,22 @@ EmitImmediate(const MCOperand &DispOp, unsigned Size,
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return;
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}
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// FIXME: Pass in the relocation type.
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#if 0
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unsigned RelocType = Is64BitMode ?
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(IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
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: (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
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#endif
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// FIXME: Pass in the relocation type, this is just a hack..
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unsigned FixupKind;
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if (Size == 1)
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FixupKind = X86::fixup_1byte_imm;
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else if (Size == 2)
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FixupKind = X86::fixup_2byte_imm;
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else if (Size == 4)
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FixupKind = X86::fixup_4byte_imm;
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else {
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assert(Size == 8 && "Unknown immediate size");
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FixupKind = X86::fixup_8byte_imm;
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}
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// Emit a symbolic constant as a fixup and 4 zeros.
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Fixups.push_back(MCFixup::Create(CurByte, DispOp.getExpr(),
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MCFixupKind(X86::reloc_absolute_word)));
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MCFixupKind(FixupKind)));
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EmitConstant(0, Size, CurByte, OS);
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}
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@ -204,7 +209,7 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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// Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
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if (Disp.isImm() && isDisp8(Disp.getImm())) {
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EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
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EmitConstant(Disp.getImm(), 1, CurByte, OS);
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EmitImmediate(Disp, 1, CurByte, OS, Fixups);
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return;
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}
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@ -477,41 +482,20 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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case X86II::MRMInitReg:
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assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
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default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
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assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
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case X86II::RawFrm: {
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assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
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case X86II::RawFrm:
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EmitByte(BaseOpcode, CurByte, OS);
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if (CurOp == NumOps)
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break;
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assert(0 && "Unimpl RawFrm expr");
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break;
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}
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case X86II::AddRegFrm: {
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case X86II::AddRegFrm:
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EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
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if (CurOp == NumOps)
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break;
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const MCOperand &MO1 = MI.getOperand(CurOp++);
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if (MO1.isImm()) {
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unsigned Size = X86II::getSizeOfImm(TSFlags);
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EmitConstant(MO1.getImm(), Size, CurByte, OS);
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break;
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}
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assert(0 && "Unimpl AddRegFrm expr");
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break;
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}
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case X86II::MRMDestReg:
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EmitByte(BaseOpcode, CurByte, OS);
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EmitRegModRMByte(MI.getOperand(CurOp),
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GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
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CurOp += 2;
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if (CurOp != NumOps)
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EmitConstant(MI.getOperand(CurOp++).getImm(),
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X86II::getSizeOfImm(TSFlags), CurByte, OS);
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break;
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case X86II::MRMDestMem:
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@ -520,9 +504,6 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
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CurByte, OS, Fixups);
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CurOp += X86AddrNumOperands + 1;
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if (CurOp != NumOps)
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EmitConstant(MI.getOperand(CurOp++).getImm(),
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X86II::getSizeOfImm(TSFlags), CurByte, OS);
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break;
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case X86II::MRMSrcReg:
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@ -530,9 +511,6 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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EmitRegModRMByte(MI.getOperand(CurOp+1), GetX86RegNum(MI.getOperand(CurOp)),
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CurByte, OS);
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CurOp += 2;
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if (CurOp != NumOps)
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EmitConstant(MI.getOperand(CurOp++).getImm(),
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X86II::getSizeOfImm(TSFlags), CurByte, OS);
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break;
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case X86II::MRMSrcMem: {
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@ -549,16 +527,13 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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EmitMemModRMByte(MI, CurOp+1, GetX86RegNum(MI.getOperand(CurOp)),
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CurByte, OS, Fixups);
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CurOp += AddrOperands + 1;
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if (CurOp != NumOps)
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EmitConstant(MI.getOperand(CurOp++).getImm(),
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X86II::getSizeOfImm(TSFlags), CurByte, OS);
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break;
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}
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case X86II::MRM0r: case X86II::MRM1r:
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case X86II::MRM2r: case X86II::MRM3r:
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case X86II::MRM4r: case X86II::MRM5r:
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case X86II::MRM6r: case X86II::MRM7r: {
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case X86II::MRM6r: case X86II::MRM7r:
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EmitByte(BaseOpcode, CurByte, OS);
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// Special handling of lfence, mfence, monitor, and mwait.
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@ -578,73 +553,23 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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(TSFlags & X86II::FormMask)-X86II::MRM0r,
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CurByte, OS);
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}
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if (CurOp == NumOps)
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break;
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const MCOperand &MO1 = MI.getOperand(CurOp++);
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if (MO1.isImm()) {
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EmitConstant(MO1.getImm(), X86II::getSizeOfImm(TSFlags), CurByte, OS);
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break;
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}
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assert(0 && "relo unimpl");
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#if 0
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unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
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: (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
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if (Opcode == X86::MOV64ri32)
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rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
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if (MO1.isGlobal()) {
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bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
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emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
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Indirect);
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} else if (MO1.isSymbol())
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emitExternalSymbolAddress(MO1.getSymbolName(), rt);
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else if (MO1.isCPI())
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emitConstPoolAddress(MO1.getIndex(), rt);
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else if (MO1.isJTI())
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emitJumpTableAddress(MO1.getIndex(), rt);
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break;
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#endif
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}
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case X86II::MRM0m: case X86II::MRM1m:
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case X86II::MRM2m: case X86II::MRM3m:
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case X86II::MRM4m: case X86II::MRM5m:
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case X86II::MRM6m: case X86II::MRM7m: {
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case X86II::MRM6m: case X86II::MRM7m:
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EmitByte(BaseOpcode, CurByte, OS);
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EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
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CurByte, OS, Fixups);
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CurOp += X86AddrNumOperands;
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if (CurOp == NumOps)
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break;
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const MCOperand &MO = MI.getOperand(CurOp++);
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if (MO.isImm()) {
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EmitConstant(MO.getImm(), X86II::getSizeOfImm(TSFlags), CurByte, OS);
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break;
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}
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assert(0 && "relo not handled");
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#if 0
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unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
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: (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
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if (Opcode == X86::MOV64mi32)
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rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
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if (MO.isGlobal()) {
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bool Indirect = gvNeedsNonLazyPtr(MO, TM);
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emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
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Indirect);
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} else if (MO.isSymbol())
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emitExternalSymbolAddress(MO.getSymbolName(), rt);
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else if (MO.isCPI())
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emitConstPoolAddress(MO.getIndex(), rt);
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else if (MO.isJTI())
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emitJumpTableAddress(MO.getIndex(), rt);
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#endif
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break;
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}
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}
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// If there is a remaining operand, it must be a trailing immediate. Emit it
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// according to the right size for the instruction.
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if (CurOp != NumOps)
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EmitImmediate(MI.getOperand(CurOp++), X86II::getSizeOfImm(TSFlags),
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CurByte, OS, Fixups);
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#ifndef NDEBUG
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// FIXME: Verify.
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