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Move isSubRegOf into MRegisterInfo. Fix a missed move elimination in LowerSubregs and add more debugging output there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41005 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -360,6 +360,17 @@ public:
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return get(RegNo).SuperRegs;
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}
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/// isSubRegOf - Predicate which returns true if RegA is a sub-register of
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/// RegB. Returns false otherwise.
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///
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bool isSubRegOf(unsigned RegA, unsigned RegB) const {
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const TargetRegisterDesc &RD = (*this)[RegA];
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for (const unsigned *reg = RD.SuperRegs; *reg != 0; ++reg)
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if (*reg == RegB)
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return true;
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return false;
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}
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/// getName - Return the symbolic target specific name for the specified
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/// physical register.
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const char *getName(unsigned RegNo) const {
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@ -59,17 +59,6 @@ static const TargetRegisterClass *getPhysicalRegisterRegClass(
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return 0;
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}
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static bool isSubRegOf(const MRegisterInfo &MRI,
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unsigned SubReg,
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unsigned SupReg) {
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const TargetRegisterDesc &RD = MRI[SubReg];
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for (const unsigned *reg = RD.SuperRegs; *reg != 0; ++reg)
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if (*reg == SupReg)
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return true;
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return false;
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}
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bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
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MachineBasicBlock *MBB = MI->getParent();
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MachineFunction &MF = *MBB->getParent();
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@ -105,7 +94,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
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}
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DOUT << "\n";
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MBB->erase(MI);
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MBB->remove(MI);
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return true;
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}
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@ -157,8 +146,8 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
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// of the destination, we copy the subreg into the source
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// However, this is only safe if the insert instruction is the kill
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// of the source register
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bool revCopyOrder = isSubRegOf(MRI, InsReg, DstReg);
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if (revCopyOrder) {
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bool revCopyOrder = MRI.isSubRegOf(InsReg, DstReg);
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if (revCopyOrder && InsReg != DstSubReg) {
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if (MI->getOperand(1).isKill()) {
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DstSubReg = MRI.getSubReg(SrcReg, SubIdx);
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// Insert sub-register copy
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@ -168,14 +157,21 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
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} else {
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TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
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}
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MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1);
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#ifndef NDEBUG
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MachineBasicBlock::iterator dMI = MI;
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DOUT << "subreg: " << *(--dMI);
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#endif
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} else {
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assert(0 && "Don't know how to convert this insert");
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}
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}
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#ifndef NDEBUG
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if (InsReg == DstSubReg) {
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DOUT << "subreg: Eliminated subreg copy\n";
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}
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#endif
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if (SrcReg != DstReg) {
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// Insert super-register copy
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@ -189,10 +185,19 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
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"Insert superreg and Dst must be of same register class");
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MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0);
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#ifndef NDEBUG
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MachineBasicBlock::iterator dMI = MI;
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DOUT << "subreg: " << *(--dMI);
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#endif
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}
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#ifndef NDEBUG
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if (SrcReg == DstReg) {
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DOUT << "subreg: Eliminated superreg copy\n";
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}
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#endif
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if (!revCopyOrder && InsReg != DstSubReg) {
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// Insert sub-register copy
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const TargetRegisterClass *TRC1 = 0;
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@ -201,14 +206,16 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
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} else {
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TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
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}
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MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1);
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#ifndef NDEBUG
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MachineBasicBlock::iterator dMI = MI;
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DOUT << "subreg: " << *(--dMI);
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#endif
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}
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DOUT << "\n";
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MBB->erase(MI);
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MBB->remove(MI);
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return true;
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}
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