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MC: Update MCFixup naming. NFC.

Browse Source 
s/MCFixup::Create/MCFixup::create/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237468 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2015-05-15 19:13:05 +00:00
parent 0048c06a9d
commit 8b22e9c00a
14 changed files with 61 additions and 61 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/MC/MCFixup.h
View File

@ -75,7 +75,7 @@ class MCFixup {
/// The source location which gave rise to the fixup, if any.
SMLoc Loc;
public:
static MCFixup Create(uint32_t Offset, const MCExpr *Value,
static MCFixup create(uint32_t Offset, const MCExpr *Value,
MCFixupKind Kind, SMLoc Loc = SMLoc()) {
assert(unsigned(Kind) < MaxTargetFixupKind && "Kind out of range!");
MCFixup FI;

6
lib/MC/MCObjectStreamer.cpp
View File

@ -120,7 +120,7 @@ void MCObjectStreamer::EmitValueImpl(const MCExpr *Value, unsigned Size,
return;
}
DF->getFixups().push_back(
MCFixup::Create(DF->getContents().size(), Value,
MCFixup::create(DF->getContents().size(), Value,
MCFixup::getKindForSize(Size, false), Loc));
DF->getContents().resize(DF->getContents().size() + Size, 0);
}
@ -393,7 +393,7 @@ bool MCObjectStreamer::EmitValueToOffset(const MCExpr *Offset,
void MCObjectStreamer::EmitGPRel32Value(const MCExpr *Value) {
MCDataFragment *DF = getOrCreateDataFragment();
DF->getFixups().push_back(MCFixup::Create(DF->getContents().size(),
DF->getFixups().push_back(MCFixup::create(DF->getContents().size(),
Value, FK_GPRel_4));
DF->getContents().resize(DF->getContents().size() + 4, 0);
}
@ -402,7 +402,7 @@ void MCObjectStreamer::EmitGPRel32Value(const MCExpr *Value) {
void MCObjectStreamer::EmitGPRel64Value(const MCExpr *Value) {
MCDataFragment *DF = getOrCreateDataFragment();
DF->getFixups().push_back(MCFixup::Create(DF->getContents().size(),
DF->getFixups().push_back(MCFixup::create(DF->getContents().size(),
Value, FK_GPRel_4));
DF->getContents().resize(DF->getContents().size() + 8, 0);
}

4
lib/MC/WinCOFFStreamer.cpp
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@ -161,7 +161,7 @@ void MCWinCOFFStreamer::EndCOFFSymbolDef() {
void MCWinCOFFStreamer::EmitCOFFSectionIndex(MCSymbol const *Symbol) {
MCDataFragment *DF = getOrCreateDataFragment();
const MCSymbolRefExpr *SRE = MCSymbolRefExpr::Create(Symbol, getContext());
MCFixup Fixup = MCFixup::Create(DF->getContents().size(), SRE, FK_SecRel_2);
MCFixup Fixup = MCFixup::create(DF->getContents().size(), SRE, FK_SecRel_2);
DF->getFixups().push_back(Fixup);
DF->getContents().resize(DF->getContents().size() + 2, 0);
}
@ -169,7 +169,7 @@ void MCWinCOFFStreamer::EmitCOFFSectionIndex(MCSymbol const *Symbol) {
void MCWinCOFFStreamer::EmitCOFFSecRel32(MCSymbol const *Symbol) {
MCDataFragment *DF = getOrCreateDataFragment();
const MCSymbolRefExpr *SRE = MCSymbolRefExpr::Create(Symbol, getContext());
MCFixup Fixup = MCFixup::Create(DF->getContents().size(), SRE, FK_SecRel_4);
MCFixup Fixup = MCFixup::create(DF->getContents().size(), SRE, FK_SecRel_4);
DF->getFixups().push_back(Fixup);
DF->getContents().resize(DF->getContents().size() + 4, 0);
}

18
lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
View File

@ -232,7 +232,7 @@ AArch64MCCodeEmitter::getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
else {
assert(MO.isExpr() && "unable to encode load/store imm operand");
MCFixupKind Kind = MCFixupKind(FixupKind);
Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
++MCNumFixups;
}
@ -256,7 +256,7 @@ AArch64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
MCFixupKind Kind = MI.getOpcode() == AArch64::ADR
? MCFixupKind(AArch64::fixup_aarch64_pcrel_adr_imm21)
: MCFixupKind(AArch64::fixup_aarch64_pcrel_adrp_imm21);
Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
MCNumFixups += 1;
@ -286,7 +286,7 @@ AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
// Encode the 12 bits of the fixup.
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_add_imm12);
Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
++MCNumFixups;
@ -306,7 +306,7 @@ uint32_t AArch64MCCodeEmitter::getCondBranchTargetOpValue(
assert(MO.isExpr() && "Unexpected target type!");
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch19);
Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
++MCNumFixups;
@ -328,7 +328,7 @@ AArch64MCCodeEmitter::getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
assert(MO.isExpr() && "Unexpected target type!");
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_ldr_pcrel_imm19);
Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
++MCNumFixups;
@ -355,7 +355,7 @@ AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
return MO.getImm();
assert(MO.isExpr() && "Unexpected movz/movk immediate");
Fixups.push_back(MCFixup::Create(
Fixups.push_back(MCFixup::create(
0, MO.getExpr(), MCFixupKind(AArch64::fixup_aarch64_movw), MI.getLoc()));
++MCNumFixups;
@ -376,7 +376,7 @@ uint32_t AArch64MCCodeEmitter::getTestBranchTargetOpValue(
assert(MO.isExpr() && "Unexpected ADR target type!");
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch14);
Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
++MCNumFixups;
@ -400,7 +400,7 @@ AArch64MCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
MCFixupKind Kind = MI.getOpcode() == AArch64::BL
? MCFixupKind(AArch64::fixup_aarch64_pcrel_call26)
: MCFixupKind(AArch64::fixup_aarch64_pcrel_branch26);
Fixups.push_back(MCFixup::Create(0, MO.getExpr(), Kind, MI.getLoc()));
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
++MCNumFixups;
@ -606,7 +606,7 @@ void AArch64MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
// following (BLR) instruction. It doesn't emit any code itself so it
// doesn't go through the normal TableGenerated channels.
MCFixupKind Fixup = MCFixupKind(AArch64::fixup_aarch64_tlsdesc_call);
Fixups.push_back(MCFixup::Create(0, MI.getOperand(0).getExpr(), Fixup));
Fixups.push_back(MCFixup::create(0, MI.getOperand(0).getExpr(), Fixup));
return;
}

4
lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
View File

@ -1056,7 +1056,7 @@ inline void ARMELFStreamer::SwitchToExIdxSection(const MCSymbol &FnStart) {
}
void ARMELFStreamer::EmitFixup(const MCExpr *Expr, MCFixupKind Kind) {
MCDataFragment *Frag = getOrCreateDataFragment();
Frag->getFixups().push_back(MCFixup::Create(Frag->getContents().size(), Expr,
Frag->getFixups().push_back(MCFixup::create(Frag->getContents().size(), Expr,
Kind));
}
@ -1144,7 +1144,7 @@ void ARMELFStreamer::EmitPersonalityFixup(StringRef Name) {
visitUsedExpr(*PersonalityRef);
MCDataFragment *DF = getOrCreateDataFragment();
DF->getFixups().push_back(MCFixup::Create(DF->getContents().size(),
DF->getFixups().push_back(MCFixup::create(DF->getContents().size(),
PersonalityRef,
MCFixup::getKindForSize(4, false)));
}

16
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -287,7 +287,7 @@ public:
// See ARMELFObjectWriter::ExplicitRelSym and
// ARMELFObjectWriter::GetRelocTypeInner for more details.
MCFixupKind Kind = MCFixupKind(FK_Data_4);
Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
return 0;
}
@ -318,7 +318,7 @@ public:
// See ARMELFObjectWriter::ExplicitRelSym and
// ARMELFObjectWriter::GetRelocTypeInner for more details.
MCFixupKind Kind = MCFixupKind(FK_Data_4);
Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
return 0;
}
@ -595,7 +595,7 @@ static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
assert(MO.isExpr() && "Unexpected branch target type!");
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(FixupKind);
Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
// All of the information is in the fixup.
return 0;
@ -900,7 +900,7 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
else
Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
++MCNumCPRelocations;
} else {
@ -979,7 +979,7 @@ getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
assert(MO.isExpr() && "Unexpected machine operand type!");
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
++MCNumCPRelocations;
} else
@ -1058,7 +1058,7 @@ ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
break;
}
Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));
Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
return 0;
}
// If the expression doesn't have :upper16: or :lower16: on it,
@ -1194,7 +1194,7 @@ getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
assert(MO.isExpr() && "Unexpected machine operand type!");
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
++MCNumCPRelocations;
return (Rn << 9) | (1 << 13);
@ -1276,7 +1276,7 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
else
Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
++MCNumCPRelocations;
} else {

6
lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp
View File

@ -81,12 +81,12 @@ unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI,
if (MI.getOpcode() == BPF::JAL)
// func call name
Fixups.push_back(MCFixup::Create(0, Expr, FK_SecRel_4));
Fixups.push_back(MCFixup::create(0, Expr, FK_SecRel_4));
else if (MI.getOpcode() == BPF::LD_imm64)
Fixups.push_back(MCFixup::Create(0, Expr, FK_SecRel_8));
Fixups.push_back(MCFixup::create(0, Expr, FK_SecRel_8));
else
// bb label
Fixups.push_back(MCFixup::Create(0, Expr, FK_PCRel_2));
Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_2));
return 0;
}

2
lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
View File

@ -494,7 +494,7 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
}
MCFixup fixup =
MCFixup::Create(*Addend, MO.getExpr(), MCFixupKind(FixupKind));
MCFixup::create(*Addend, MO.getExpr(), MCFixupKind(FixupKind));
Fixups.push_back(fixup);
// All of the information is in the fixup.
return (0);

24
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
View File

@ -226,7 +226,7 @@ getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
"getBranchTargetOpValue expects only expressions or immediates");
const MCExpr *Expr = MO.getExpr();
Fixups.push_back(MCFixup::Create(0, Expr,
Fixups.push_back(MCFixup::create(0, Expr,
MCFixupKind(Mips::fixup_Mips_PC16)));
return 0;
}
@ -248,7 +248,7 @@ getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
"getBranchTargetOpValueMM expects only expressions or immediates");
const MCExpr *Expr = MO.getExpr();
Fixups.push_back(MCFixup::Create(0, Expr,
Fixups.push_back(MCFixup::create(0, Expr,
MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
return 0;
}
@ -270,7 +270,7 @@ getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
"getBranchTargetOpValuePC10 expects only expressions or immediates");
const MCExpr *Expr = MO.getExpr();
Fixups.push_back(MCFixup::Create(0, Expr,
Fixups.push_back(MCFixup::create(0, Expr,
MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
return 0;
}
@ -292,7 +292,7 @@ getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
"getBranchTargetOpValueMM expects only expressions or immediates");
const MCExpr *Expr = MO.getExpr();
Fixups.push_back(MCFixup::Create(0, Expr,
Fixups.push_back(MCFixup::create(0, Expr,
MCFixupKind(Mips::
fixup_MICROMIPS_PC16_S1)));
return 0;
@ -315,7 +315,7 @@ getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
"getBranchTarget21OpValue expects only expressions or immediates");
const MCExpr *Expr = MO.getExpr();
Fixups.push_back(MCFixup::Create(0, Expr,
Fixups.push_back(MCFixup::create(0, Expr,
MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
return 0;
}
@ -337,7 +337,7 @@ getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
"getBranchTarget26OpValue expects only expressions or immediates");
const MCExpr *Expr = MO.getExpr();
Fixups.push_back(MCFixup::Create(0, Expr,
Fixups.push_back(MCFixup::create(0, Expr,
MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
return 0;
}
@ -377,7 +377,7 @@ getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
"getJumpTargetOpValue expects only expressions or an immediate");
const MCExpr *Expr = MO.getExpr();
Fixups.push_back(MCFixup::Create(0, Expr,
Fixups.push_back(MCFixup::create(0, Expr,
MCFixupKind(Mips::fixup_Mips_26)));
return 0;
}
@ -395,7 +395,7 @@ getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
"getJumpTargetOpValueMM expects only expressions or an immediate");
const MCExpr *Expr = MO.getExpr();
Fixups.push_back(MCFixup::Create(0, Expr,
Fixups.push_back(MCFixup::create(0, Expr,
MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
return 0;
}
@ -501,7 +501,7 @@ getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
: Mips::fixup_Mips_LO16;
break;
}
Fixups.push_back(MCFixup::Create(0, MipsExpr, MCFixupKind(FixupKind)));
Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind)));
return 0;
}
@ -608,7 +608,7 @@ getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
break;
} // switch
Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
return 0;
}
return 0;
@ -859,7 +859,7 @@ MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
"getSimm19Lsl2Encoding expects only expressions or an immediate");
const MCExpr *Expr = MO.getExpr();
Fixups.push_back(MCFixup::Create(0, Expr,
Fixups.push_back(MCFixup::create(0, Expr,
MCFixupKind(Mips::fixup_MIPS_PC19_S2)));
return 0;
}
@ -880,7 +880,7 @@ MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
"getSimm18Lsl2Encoding expects only expressions or an immediate");
const MCExpr *Expr = MO.getExpr();
Fixups.push_back(MCFixup::Create(0, Expr,
Fixups.push_back(MCFixup::create(0, Expr,
MCFixupKind(Mips::fixup_MIPS_PC18_S3)));
return 0;
}

18
lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
View File

@ -174,7 +174,7 @@ getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
// Add a fixup for the branch target.
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_br24));
return 0;
}
@ -186,7 +186,7 @@ unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
// Add a fixup for the branch target.
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_brcond14));
return 0;
}
@ -199,7 +199,7 @@ getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
// Add a fixup for the branch target.
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_br24abs));
return 0;
}
@ -212,7 +212,7 @@ getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
// Add a fixup for the branch target.
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_brcond14abs));
return 0;
}
@ -224,7 +224,7 @@ unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
// Add a fixup for the immediate field.
Fixups.push_back(MCFixup::Create(IsLittleEndian? 0 : 2, MO.getExpr(),
Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_half16));
return 0;
}
@ -242,7 +242,7 @@ unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
// Add a fixup for the displacement field.
Fixups.push_back(MCFixup::Create(IsLittleEndian? 0 : 2, MO.getExpr(),
Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_half16));
return RegBits;
}
@ -261,7 +261,7 @@ unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
// Add a fixup for the displacement field.
Fixups.push_back(MCFixup::Create(IsLittleEndian? 0 : 2, MO.getExpr(),
Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_half16ds));
return RegBits;
}
@ -324,7 +324,7 @@ unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
// Add a fixup for the TLS register, which simply provides a relocation
// hint to the linker that this statement is part of a relocation sequence.
// Return the thread-pointer register's encoding.
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_nofixup));
Triple TT(STI.getTargetTriple());
bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le;
@ -338,7 +338,7 @@ unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
// (__tls_get_addr), which we create via getDirectBrEncoding as usual,
// and one for the TLSGD or TLSLD symbol, which is emitted here.
const MCOperand &MO = MI.getOperand(OpNo+1);
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_nofixup));
return getDirectBrEncoding(MI, OpNo, Fixups, STI);
}

4
lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp
View File

@ -234,7 +234,7 @@ unsigned SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
if (MO.isExpr()) {
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;
Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
return 0;
}
@ -261,7 +261,7 @@ uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
// This is used for constant data stored in .rodata.
Kind = (MCFixupKind)AMDGPU::fixup_si_rodata;
}
Fixups.push_back(MCFixup::Create(4, Expr, Kind, MI.getLoc()));
Fixups.push_back(MCFixup::create(4, Expr, Kind, MI.getLoc()));
}
// Figure out the operand number, needed for isSrcOperand check

12
lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
View File

@ -132,7 +132,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
const MCExpr *Expr = MO.getExpr();
if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind();
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
Fixups.push_back(MCFixup::create(0, Expr, Kind));
return 0;
}
@ -174,7 +174,7 @@ getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
fixupKind = (MCFixupKind)Sparc::fixup_sparc_wplt30;
}
Fixups.push_back(MCFixup::Create(0, MO.getExpr(), fixupKind));
Fixups.push_back(MCFixup::create(0, MO.getExpr(), fixupKind));
return 0;
}
@ -187,7 +187,7 @@ getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
if (MO.isReg() || MO.isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
(MCFixupKind)Sparc::fixup_sparc_br22));
return 0;
}
@ -200,7 +200,7 @@ getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
if (MO.isReg() || MO.isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
(MCFixupKind)Sparc::fixup_sparc_br19));
return 0;
}
@ -212,9 +212,9 @@ getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
if (MO.isReg() || MO.isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
(MCFixupKind)Sparc::fixup_sparc_br16_2));
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
(MCFixupKind)Sparc::fixup_sparc_br16_14));
return 0;

4
lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
View File

@ -227,12 +227,12 @@ SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum,
Expr = MCBinaryExpr::CreateAdd(Expr, OffsetExpr, Ctx);
}
}
Fixups.push_back(MCFixup::Create(Offset, Expr, (MCFixupKind)Kind));
Fixups.push_back(MCFixup::create(Offset, Expr, (MCFixupKind)Kind));
// Output the fixup for the TLS marker if present.
if (AllowTLS && OpNum + 1 < MI.getNumOperands()) {
const MCOperand &MOTLS = MI.getOperand(OpNum + 1);
Fixups.push_back(MCFixup::Create(0, MOTLS.getExpr(),
Fixups.push_back(MCFixup::create(0, MOTLS.getExpr(),
(MCFixupKind)SystemZ::FK_390_TLS_CALL));
}
return 0;

2
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
View File

@ -355,7 +355,7 @@ EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size,
Ctx);
// Emit a symbolic constant as a fixup and 4 zeros.
Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind, Loc));
Fixups.push_back(MCFixup::create(CurByte, Expr, FixupKind, Loc));
EmitConstant(0, Size, CurByte, OS);
}