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Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.

Browse Source 
This update was done with the following bash script:

  find test/CodeGen -name "*.ll" | \
  while read NAME; do
    echo "$NAME"
    if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
      TEMP=`mktemp -t temp`
      cp $NAME $TEMP
      sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
      while read FUNC; do
        sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
      done
      sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
      sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
      sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
      sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
      mv $TEMP $NAME
    fi
  done


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Stephen Lin
2013-07-14 06:24:09 +00:00
parent 6611eaa32f
commit 8b2b8a1835
937 changed files with 8028 additions and 8028 deletions
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12
test/CodeGen/PowerPC/vec_extload.ll
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@@ -14,7 +14,7 @@ define <16 x i8> @v16si8_sext_in_reg(<16 x i8> %a) {
%c = sext <16 x i4> %b to <16 x i8>
ret <16 x i8> %c
}
; CHECK: v16si8_sext_in_reg:
; CHECK-LABEL: v16si8_sext_in_reg:
; CHECK: vslb
; CHECK: vsrab
; CHECK: blr
@@ -26,7 +26,7 @@ define <16 x i8> @v16si8_zext_in_reg(<16 x i8> %a) {
%c = zext <16 x i4> %b to <16 x i8>
ret <16 x i8> %c
}
; CHECK: v16si8_zext_in_reg:
; CHECK-LABEL: v16si8_zext_in_reg:
; CHECK: vspltisb [[VMASK:[0-9]+]], 15
; CHECK-NEXT: vand 2, 2, [[VMASK]]
@@ -36,7 +36,7 @@ define <8 x i16> @v8si16_sext_in_reg(<8 x i16> %a) {
%c = sext <8 x i8> %b to <8 x i16>
ret <8 x i16> %c
}
; CHECK: v8si16_sext_in_reg:
; CHECK-LABEL: v8si16_sext_in_reg:
; CHECK: vslh
; CHECK: vsrah
; CHECK: blr
@@ -48,7 +48,7 @@ define <8 x i16> @v8si16_zext_in_reg(<8 x i16> %a) {
%c = zext <8 x i8> %b to <8 x i16>
ret <8 x i16> %c
}
; CHECK: v8si16_zext_in_reg:
; CHECK-LABEL: v8si16_zext_in_reg:
; CHECK: ld [[RMASKTOC:[0-9]+]], .LC{{[0-9]+}}@toc(2)
; CHECK-NEXT: lvx [[VMASK:[0-9]+]], {{[0-9]+}}, [[RMASKTOC]]
; CHECK-NEXT: vand 2, 2, [[VMASK]]
@@ -60,7 +60,7 @@ define <4 x i32> @v4si32_sext_in_reg(<4 x i32> %a) {
%c = sext <4 x i16> %b to <4 x i32>
ret <4 x i32> %c
}
; CHECK: v4si32_sext_in_reg:
; CHECK-LABEL: v4si32_sext_in_reg:
; CHECK: vslw
; CHECK: vsraw
; CHECK: blr
@@ -71,7 +71,7 @@ define <4 x i32> @v4si32_zext_in_reg(<4 x i32> %a) {
%c = zext <4 x i16> %b to <4 x i32>
ret <4 x i32> %c
}
; CHECK: v4si32_zext_in_reg:
; CHECK-LABEL: v4si32_zext_in_reg:
; CHECK: vspltisw [[VMASK:[0-9]+]], -16
; CHECK-NEXT: vsrw [[VMASK]], [[VMASK]], [[VMASK]]
; CHECK-NEXT: vand 2, 2, [[VMASK]]