6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-21 02:29:22 +00:00
Code Issues Projects Releases Wiki Activity

Don't set kill flags for instructions which the scheduler has cloned.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103827 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2010-05-14 22:01:14 +00:00
parent 4ee637c730
commit 8b3a8f5773
2 changed files with 34 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
lib/CodeGen/SelectionDAG/InstrEmitter.cpp
View File

@ -265,7 +265,7 @@ InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
unsigned IIOpNum, unsigned IIOpNum,
const TargetInstrDesc *II, const TargetInstrDesc *II,
DenseMap<SDValue, unsigned> &VRBaseMap, DenseMap<SDValue, unsigned> &VRBaseMap,
bool IsDebug) { bool IsDebug, bool IsClone, bool IsCloned) {
assert(Op.getValueType() != MVT::Other && assert(Op.getValueType() != MVT::Other &&
Op.getValueType() != MVT::Flag && Op.getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!"); "Chain and flag operands should occur at end of operand list!");
@ -299,11 +299,14 @@ InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
// If this value has only one use, that use is a kill. This is a // If this value has only one use, that use is a kill. This is a
// conservative approximation. InstrEmitter does trivial coalescing // conservative approximation. InstrEmitter does trivial coalescing
// with CopyFromReg nodes, so don't emit kill flags for them. // with CopyFromReg nodes, so don't emit kill flags for them.
// Avoid kill flags on Schedule cloned nodes, since there will be
// multiple uses.
// Tied operands are never killed, so we need to check that. And that // Tied operands are never killed, so we need to check that. And that
// means we need to determine the index of the operand. // means we need to determine the index of the operand.
bool isKill = Op.hasOneUse() && bool isKill = Op.hasOneUse() &&
Op.getNode()->getOpcode() != ISD::CopyFromReg && Op.getNode()->getOpcode() != ISD::CopyFromReg &&
!IsDebug; !IsDebug &&
!(IsClone || IsCloned);
if (isKill) { if (isKill) {
unsigned Idx = MI->getNumOperands(); unsigned Idx = MI->getNumOperands();
while (Idx > 0 && while (Idx > 0 &&
@ -329,9 +332,10 @@ void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
unsigned IIOpNum, unsigned IIOpNum,
const TargetInstrDesc *II, const TargetInstrDesc *II,
DenseMap<SDValue, unsigned> &VRBaseMap, DenseMap<SDValue, unsigned> &VRBaseMap,
bool IsDebug) { bool IsDebug, bool IsClone, bool IsCloned) {
if (Op.isMachineOpcode()) { if (Op.isMachineOpcode()) {
AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug); AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
IsDebug, IsClone, IsCloned);
} else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); MI->addOperand(MachineOperand::CreateImm(C->getSExtValue()));
} else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
@ -380,7 +384,8 @@ void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
assert(Op.getValueType() != MVT::Other && assert(Op.getValueType() != MVT::Other &&
Op.getValueType() != MVT::Flag && Op.getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!"); "Chain and flag operands should occur at end of operand list!");
AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug); AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
IsDebug, IsClone, IsCloned);
} }
} }
@ -402,7 +407,8 @@ getSuperRegisterRegClass(const TargetRegisterClass *TRC,
/// EmitSubregNode - Generate machine code for subreg nodes. /// EmitSubregNode - Generate machine code for subreg nodes.
/// ///
void InstrEmitter::EmitSubregNode(SDNode *Node, void InstrEmitter::EmitSubregNode(SDNode *Node,
DenseMap<SDValue, unsigned> &VRBaseMap){ DenseMap<SDValue, unsigned> &VRBaseMap,
bool IsClone, bool IsCloned) {
unsigned VRBase = 0; unsigned VRBase = 0;
unsigned Opc = Node->getMachineOpcode(); unsigned Opc = Node->getMachineOpcode();
@ -446,7 +452,8 @@ void InstrEmitter::EmitSubregNode(SDNode *Node,
// Add def, source, and subreg index // Add def, source, and subreg index
MI->addOperand(MachineOperand::CreateReg(VRBase, true)); MI->addOperand(MachineOperand::CreateReg(VRBase, true));
AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap, /*IsDebug=*/false,
IsClone, IsCloned);
MI->addOperand(MachineOperand::CreateImm(SubIdx)); MI->addOperand(MachineOperand::CreateImm(SubIdx));
MBB->insert(InsertPos, MI); MBB->insert(InsertPos, MI);
} else if (Opc == TargetOpcode::INSERT_SUBREG || } else if (Opc == TargetOpcode::INSERT_SUBREG ||
@ -480,9 +487,11 @@ void InstrEmitter::EmitSubregNode(SDNode *Node,
const ConstantSDNode *SD = cast<ConstantSDNode>(N0); const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue())); MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
} else } else
AddOperand(MI, N0, 0, 0, VRBaseMap); AddOperand(MI, N0, 0, 0, VRBaseMap, /*IsDebug=*/false,
IsClone, IsCloned);
// Add the subregster being inserted // Add the subregster being inserted
AddOperand(MI, N1, 0, 0, VRBaseMap); AddOperand(MI, N1, 0, 0, VRBaseMap, /*IsDebug=*/false,
IsClone, IsCloned);
MI->addOperand(MachineOperand::CreateImm(SubIdx)); MI->addOperand(MachineOperand::CreateImm(SubIdx));
MBB->insert(InsertPos, MI); MBB->insert(InsertPos, MI);
} else } else
@ -524,7 +533,8 @@ InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
/// ///
void InstrEmitter::EmitRegSequence(SDNode *Node, void InstrEmitter::EmitRegSequence(SDNode *Node,
DenseMap<SDValue, unsigned> &VRBaseMap) { DenseMap<SDValue, unsigned> &VRBaseMap,
bool IsClone, bool IsCloned) {
const TargetRegisterClass *RC = TLI->getRegClassFor(Node->getValueType(0)); const TargetRegisterClass *RC = TLI->getRegClassFor(Node->getValueType(0));
unsigned NewVReg = MRI->createVirtualRegister(RC); unsigned NewVReg = MRI->createVirtualRegister(RC);
MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
@ -545,7 +555,8 @@ void InstrEmitter::EmitRegSequence(SDNode *Node,
assert(SRC == RC && "Invalid subregister index in REG_SEQUENCE"); assert(SRC == RC && "Invalid subregister index in REG_SEQUENCE");
} }
#endif #endif
AddOperand(MI, Op, i+1, &II, VRBaseMap); AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
IsClone, IsCloned);
} }
MBB->insert(InsertPos, MI); MBB->insert(InsertPos, MI);
@ -586,7 +597,7 @@ InstrEmitter::EmitDbgValue(SDDbgValue *SD,
MIB.addReg(0U); // undef MIB.addReg(0U); // undef
else else
AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
true /*IsDebug*/); /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
} else if (SD->getKind() == SDDbgValue::CONST) { } else if (SD->getKind() == SDDbgValue::CONST) {
const Value *V = SD->getConst(); const Value *V = SD->getConst();
if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
@ -625,7 +636,7 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
if (Opc == TargetOpcode::EXTRACT_SUBREG || if (Opc == TargetOpcode::EXTRACT_SUBREG ||
Opc == TargetOpcode::INSERT_SUBREG || Opc == TargetOpcode::INSERT_SUBREG ||
Opc == TargetOpcode::SUBREG_TO_REG) { Opc == TargetOpcode::SUBREG_TO_REG) {
EmitSubregNode(Node, VRBaseMap); EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
return; return;
} }
@ -637,7 +648,7 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
// Handle REG_SEQUENCE specially. // Handle REG_SEQUENCE specially.
if (Opc == TargetOpcode::REG_SEQUENCE) { if (Opc == TargetOpcode::REG_SEQUENCE) {
EmitRegSequence(Node, VRBaseMap); EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
return; return;
} }
@ -676,7 +687,7 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
for (unsigned i = NumSkip; i != NodeOperands; ++i) for (unsigned i = NumSkip; i != NodeOperands; ++i)
AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
VRBaseMap); VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
// Transfer all of the memory reference descriptions of this instruction. // Transfer all of the memory reference descriptions of this instruction.
MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
@ -823,7 +834,8 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
// The addressing mode has been selected, just add all of the // The addressing mode has been selected, just add all of the
// operands to the machine instruction. // operands to the machine instruction.
for (; NumVals; --NumVals, ++i) for (; NumVals; --NumVals, ++i)
AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap); AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap,
/*IsDebug=*/false, IsClone, IsCloned);
break; break;
} }
} }

10
lib/CodeGen/SelectionDAG/InstrEmitter.h
View File

@ -65,7 +65,7 @@ class InstrEmitter {
unsigned IIOpNum, unsigned IIOpNum,
const TargetInstrDesc *II, const TargetInstrDesc *II,
DenseMap<SDValue, unsigned> &VRBaseMap, DenseMap<SDValue, unsigned> &VRBaseMap,
bool IsDebug = false); bool IsDebug, bool IsClone, bool IsCloned);
/// AddOperand - Add the specified operand to the specified machine instr. II /// AddOperand - Add the specified operand to the specified machine instr. II
/// specifies the instruction information for the node, and IIOpNum is the /// specifies the instruction information for the node, and IIOpNum is the
@ -75,11 +75,12 @@ class InstrEmitter {
unsigned IIOpNum, unsigned IIOpNum,
const TargetInstrDesc *II, const TargetInstrDesc *II,
DenseMap<SDValue, unsigned> &VRBaseMap, DenseMap<SDValue, unsigned> &VRBaseMap,
bool IsDebug = false); bool IsDebug, bool IsClone, bool IsCloned);
/// EmitSubregNode - Generate machine code for subreg nodes. /// EmitSubregNode - Generate machine code for subreg nodes.
/// ///
void EmitSubregNode(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap); void EmitSubregNode(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap,
bool IsClone, bool IsCloned);
/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
/// COPY_TO_REGCLASS is just a normal copy, except that the destination /// COPY_TO_REGCLASS is just a normal copy, except that the destination
@ -90,7 +91,8 @@ class InstrEmitter {
/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
/// ///
void EmitRegSequence(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap); void EmitRegSequence(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap,
bool IsClone, bool IsCloned);
public: public:
/// CountResults - The results of target nodes have register or immediate /// CountResults - The results of target nodes have register or immediate
/// operands first, then an optional chain, and optional flag operands /// operands first, then an optional chain, and optional flag operands