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TableGen: Fix register class lane masks being too conservative.

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When calculating the lanemask of a register class we have to include the
masks of subregisters supported by any of the class members, not just
the ones supported by all class members.

This fixes problems when coalescing towards a subclass with additional
subregisters available.

The attached testcase works fine as is, but does crash if you enable
subregister liveness on x86 without this change applied.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232652 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun 2015-03-18 17:56:09 +00:00
parent df600f8049
commit 8b41add6ca
2 changed files with 30 additions and 1 deletions
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29
test/CodeGen/X86/coalescer-subreg.ll Normal file
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@ -0,0 +1,29 @@
; RUN: llc -o - %s -verify-machineinstrs
; This used to crash when coalescing a regclass like GR16 which did not support
; the sub_8bit_hi subregister with a class like GR16_ABCD that did.
target triple = "x86_64-apple-macosx10.10.0"
define void @test() #0 {
entry:
br i1 undef, label %loop, label %for.end597
loop:
%0 = load i16, i16* null, align 4
%1 = load i16, i16* undef, align 4
%or1 = or i16 %1, %0
%or2 = trunc i16 %or1 to i8
store i8 %or2, i8* undef, align 4
%2 = or i16 %1, %0
%or3 = lshr i16 %2, 8
%or4 = trunc i16 %or3 to i8
store i8 %or4, i8* undef, align 1
%3 = load i32, i32* undef, align 4
%4 = load i32, i32* undef, align 4
%or5 = or i32 %4, %3
store i32 %or5, i32* undef, align 4
store i32 0, i32* undef, align 4
br label %loop
for.end597:
ret void
}

2
utils/TableGen/CodeGenRegisters.cpp
View File

@ -1260,7 +1260,7 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
for (auto &RegClass : RegClasses) {
unsigned LaneMask = 0;
for (const auto &SubRegIndex : SubRegIndices) {
if (RegClass.getSubClassWithSubReg(&SubRegIndex) != &RegClass)
if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr)
continue;
LaneMask |= SubRegIndex.LaneMask;
}