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ARM movw/movt fixups need to mask the high bits.
The fixup value comes in as the whole 32-bit value, so for the lo16 fixup, the upper bits need to be masked off. Previously we assumed the masking had already been done and asserted. rdar://9635991 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133818 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -174,7 +174,8 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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Value >>= 16;
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// Fallthrough
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case ARM::fixup_t2_movw_lo16:
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case ARM::fixup_t2_movt_hi16_pcrel:
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case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like
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// the other hi16 fixup?
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case ARM::fixup_t2_movw_lo16_pcrel: {
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unsigned Hi4 = (Value & 0xF000) >> 12;
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unsigned i = (Value & 0x800) >> 11;
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@ -184,8 +185,10 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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// inst{26} = i;
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// inst{14-12} = Mid3;
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// inst{7-0} = Lo8;
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assert ((((int64_t)Value) >= -0x8000) && (((int64_t)Value) <= 0x7fff) &&
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"Out of range pc-relative fixup value!");
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// The value comes in as the whole thing, not just the portion required
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// for this fixup, so we need to mask off the bits not handled by this
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// portion (lo vs. hi).
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Value &= 0xffff;
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Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
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uint64_t swapped = (Value & 0xFFFF0000) >> 16;
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swapped |= (Value & 0x0000FFFF) << 16;
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