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[X86] Combine (cmov (and/or (setcc) (setcc))) into (cmov (cmov)).
Fold and/or of setcc's to double CMOV: (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2) (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2) When we can't use the CMOV instruction, it might increase branch mispredicts. When we can, or when there is no mispredict, this improves throughput and reduces register pressure. These can't be catched by generic combines, because the pattern can appear when legalizing some instructions (such as fcmp une). rdar://19767934 http://reviews.llvm.org/D7634 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231045 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ahmed Bougacha
parent
a8182029a1
commit
8b5527deef
@ -21006,6 +21006,49 @@ static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
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return SDValue();
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}
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/// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
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/// Match:
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/// (X86or (X86setcc) (X86setcc))
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/// (X86cmp (and (X86setcc) (X86setcc)), 0)
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static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
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X86::CondCode &CC1, SDValue &Flags,
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bool &isAnd) {
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if (Cond->getOpcode() == X86ISD::CMP) {
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ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
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if (!CondOp1C || !CondOp1C->isNullValue())
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return false;
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Cond = Cond->getOperand(0);
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}
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isAnd = false;
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SDValue SetCC0, SetCC1;
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switch (Cond->getOpcode()) {
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default: return false;
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case ISD::AND:
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case X86ISD::AND:
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isAnd = true;
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// fallthru
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case ISD::OR:
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case X86ISD::OR:
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SetCC0 = Cond->getOperand(0);
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SetCC1 = Cond->getOperand(1);
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break;
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};
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// Make sure we have SETCC nodes, using the same flags value.
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if (SetCC0.getOpcode() != X86ISD::SETCC ||
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SetCC1.getOpcode() != X86ISD::SETCC ||
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SetCC0->getOperand(1) != SetCC1->getOperand(1))
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return false;
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CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
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CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
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Flags = SetCC0->getOperand(1);
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return true;
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}
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/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
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static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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@ -21175,6 +21218,44 @@ static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
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}
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}
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// Fold and/or of setcc's to double CMOV:
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// (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
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// (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
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//
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// This combine lets us generate:
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// cmovcc1 (jcc1 if we don't have CMOV)
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// cmovcc2 (same)
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// instead of:
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// setcc1
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// setcc2
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// and/or
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// cmovne (jne if we don't have CMOV)
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// When we can't use the CMOV instruction, it might increase branch
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// mispredicts.
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// When we can use CMOV, or when there is no mispredict, this improves
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// throughput and reduces register pressure.
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//
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if (CC == X86::COND_NE) {
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SDValue Flags;
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X86::CondCode CC0, CC1;
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bool isAndSetCC;
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if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
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if (isAndSetCC) {
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std::swap(FalseOp, TrueOp);
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CC0 = X86::GetOppositeBranchCondition(CC0);
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CC1 = X86::GetOppositeBranchCondition(CC1);
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}
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SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, MVT::i8),
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Flags};
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SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
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SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, MVT::i8), Flags};
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SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
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DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
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return CMOV;
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}
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}
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return SDValue();
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}
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264
test/CodeGen/X86/cmovcmov.ll
Normal file
264
test/CodeGen/X86/cmovcmov.ll
Normal file
@ -0,0 +1,264 @@
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; RUN: llc < %s -asm-verbose=false -mtriple=x86_64-unknown-linux | FileCheck %s --check-prefix=CHECK --check-prefix=CMOV
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; RUN: llc < %s -asm-verbose=false -mtriple=i686-unknown-linux | FileCheck %s --check-prefix=CHECK --check-prefix=NOCMOV
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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; Test 2xCMOV patterns exposed after legalization.
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; One way to do that is with (select (fcmp une/oeq)), which gets
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; legalized to setp/setne.
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; CHECK-LABEL: test_select_fcmp_oeq_i32:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: cmovnel %esi, %edi
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; CMOV-NEXT: cmovpl %esi, %edi
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; CMOV-NEXT: movl %edi, %eax
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; CMOV-NEXT: retq
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; NOCMOV-NEXT: flds 8(%esp)
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; NOCMOV-NEXT: flds 4(%esp)
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; NOCMOV-NEXT: fucompp
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 16(%esp), %eax
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; NOCMOV-NEXT: movl %eax, %ecx
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 12(%esp), %ecx
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %ecx, %eax
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: movl (%eax), %eax
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; NOCMOV-NEXT: retl
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define i32 @test_select_fcmp_oeq_i32(float %a, float %b, i32 %c, i32 %d) #0 {
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entry:
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%cmp = fcmp oeq float %a, %b
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%r = select i1 %cmp, i32 %c, i32 %d
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ret i32 %r
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}
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; CHECK-LABEL: test_select_fcmp_oeq_i64:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: cmovneq %rsi, %rdi
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; CMOV-NEXT: cmovpq %rsi, %rdi
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; CMOV-NEXT: movq %rdi, %rax
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; CMOV-NEXT: retq
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; NOCMOV-NEXT: flds 8(%esp)
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; NOCMOV-NEXT: flds 4(%esp)
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; NOCMOV-NEXT: fucompp
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 20(%esp), %ecx
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; NOCMOV-NEXT: movl %ecx, %eax
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 12(%esp), %eax
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %eax, %ecx
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: movl (%ecx), %eax
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; NOCMOV-NEXT: orl $4, %ecx
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; NOCMOV-NEXT: movl (%ecx), %edx
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; NOCMOV-NEXT: retl
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define i64 @test_select_fcmp_oeq_i64(float %a, float %b, i64 %c, i64 %d) #0 {
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entry:
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%cmp = fcmp oeq float %a, %b
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%r = select i1 %cmp, i64 %c, i64 %d
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ret i64 %r
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}
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; CHECK-LABEL: test_select_fcmp_une_i64:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: cmovneq %rdi, %rsi
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; CMOV-NEXT: cmovpq %rdi, %rsi
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; CMOV-NEXT: movq %rsi, %rax
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; CMOV-NEXT: retq
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; NOCMOV-NEXT: flds 8(%esp)
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; NOCMOV-NEXT: flds 4(%esp)
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; NOCMOV-NEXT: fucompp
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 12(%esp), %ecx
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; NOCMOV-NEXT: movl %ecx, %eax
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 20(%esp), %eax
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %eax, %ecx
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: movl (%ecx), %eax
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; NOCMOV-NEXT: orl $4, %ecx
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; NOCMOV-NEXT: movl (%ecx), %edx
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; NOCMOV-NEXT: retl
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define i64 @test_select_fcmp_une_i64(float %a, float %b, i64 %c, i64 %d) #0 {
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entry:
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%cmp = fcmp une float %a, %b
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%r = select i1 %cmp, i64 %c, i64 %d
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ret i64 %r
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}
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; CHECK-LABEL: test_select_fcmp_oeq_f64:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: movaps %xmm3, %xmm0
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; CMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; CMOV-NEXT: movaps %xmm2, %xmm0
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; CMOV-NEXT: [[TBB1]]:
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; CMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; CMOV-NEXT: movaps %xmm0, %xmm3
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; CMOV-NEXT: [[TBB2]]:
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; CMOV-NEXT: movaps %xmm3, %xmm0
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; CMOV-NEXT: retq
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; NOCMOV-NEXT: flds 8(%esp)
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; NOCMOV-NEXT: flds 4(%esp)
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; NOCMOV-NEXT: fucompp
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 20(%esp), %eax
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; NOCMOV-NEXT: movl %eax, %ecx
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 12(%esp), %ecx
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %ecx, %eax
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: fldl (%eax)
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; NOCMOV-NEXT: retl
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define double @test_select_fcmp_oeq_f64(float %a, float %b, double %c, double %d) #0 {
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entry:
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%cmp = fcmp oeq float %a, %b
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%r = select i1 %cmp, double %c, double %d
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ret double %r
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}
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; CHECK-LABEL: test_select_fcmp_oeq_v4i32:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: movaps %xmm3, %xmm0
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; CMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; CMOV-NEXT: movaps %xmm2, %xmm0
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; CMOV-NEXT: [[TBB1]]:
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; CMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; CMOV-NEXT: movaps %xmm0, %xmm3
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; CMOV-NEXT: [[TBB2]]:
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; CMOV-NEXT: movaps %xmm3, %xmm0
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; CMOV-NEXT: retq
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; NOCMOV-NEXT: pushl %ebx
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; NOCMOV-NEXT: pushl %edi
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; NOCMOV-NEXT: pushl %esi
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; NOCMOV-NEXT: flds 24(%esp)
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; NOCMOV-NEXT: flds 20(%esp)
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; NOCMOV-NEXT: fucompp
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 44(%esp), %eax
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; NOCMOV-NEXT: movl %eax, %ecx
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 28(%esp), %ecx
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %ecx, %eax
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: movl (%eax), %eax
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; NOCMOV-NEXT: leal 48(%esp), %ecx
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; NOCMOV-NEXT: movl %ecx, %edx
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 32(%esp), %edx
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %edx, %ecx
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: movl (%ecx), %ecx
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; NOCMOV-NEXT: leal 52(%esp), %edx
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; NOCMOV-NEXT: movl %edx, %esi
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 36(%esp), %esi
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %esi, %edx
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: movl (%edx), %edx
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; NOCMOV-NEXT: leal 56(%esp), %esi
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; NOCMOV-NEXT: movl %esi, %ebx
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 40(%esp), %ebx
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: movl 16(%esp), %edi
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %ebx, %esi
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: movl (%esi), %esi
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; NOCMOV-NEXT: movl %esi, 12(%edi)
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; NOCMOV-NEXT: movl %edx, 8(%edi)
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; NOCMOV-NEXT: movl %ecx, 4(%edi)
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; NOCMOV-NEXT: movl %eax, (%edi)
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; NOCMOV-NEXT: popl %esi
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; NOCMOV-NEXT: popl %edi
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; NOCMOV-NEXT: popl %ebx
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; NOCMOV-NEXT: retl $4
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define <4 x i32> @test_select_fcmp_oeq_v4i32(float %a, float %b, <4 x i32> %c, <4 x i32> %d) #0 {
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entry:
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%cmp = fcmp oeq float %a, %b
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%r = select i1 %cmp, <4 x i32> %c, <4 x i32> %d
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ret <4 x i32> %r
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}
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; Also make sure we catch the original code-sequence of interest:
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; CMOV: [[ONE_F32_LCPI:.LCPI.*]]:
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; CMOV-NEXT: .long 1065353216
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; CHECK-LABEL: test_zext_fcmp_une:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: movss [[ONE_F32_LCPI]](%rip), %xmm0
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; CMOV-NEXT: movaps %xmm0, %xmm1
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; CMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; CMOV-NEXT: xorps %xmm1, %xmm1
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; CMOV-NEXT: [[TBB1]]:
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; CMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; CMOV-NEXT: movaps %xmm1, %xmm0
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; CMOV-NEXT: [[TBB2]]:
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; CMOV-NEXT: retq
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; NOCMOV: jne
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; NOCMOV: jp
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define float @test_zext_fcmp_une(float %a, float %b) #0 {
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entry:
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%cmp = fcmp une float %a, %b
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%conv1 = zext i1 %cmp to i32
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%conv2 = sitofp i32 %conv1 to float
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ret float %conv2
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}
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; CMOV: [[ONE_F32_LCPI:.LCPI.*]]:
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; CMOV-NEXT: .long 1065353216
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; CHECK-LABEL: test_zext_fcmp_oeq:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: xorps %xmm0, %xmm0
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; CMOV-NEXT: xorps %xmm1, %xmm1
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; CMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; CMOV-NEXT: movss [[ONE_F32_LCPI]](%rip), %xmm1
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; CMOV-NEXT: [[TBB1]]:
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; CMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; CMOV-NEXT: movaps %xmm1, %xmm0
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; CMOV-NEXT: [[TBB2]]:
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; CMOV-NEXT: retq
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; NOCMOV: jne
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; NOCMOV: jp
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define float @test_zext_fcmp_oeq(float %a, float %b) #0 {
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entry:
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%cmp = fcmp oeq float %a, %b
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%conv1 = zext i1 %cmp to i32
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%conv2 = sitofp i32 %conv1 to float
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ret float %conv2
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}
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attributes #0 = { nounwind }
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@ -1,5 +1,5 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 | FileCheck %s
|
||||
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
|
||||
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
|
||||
|
||||
; Test all the cmp predicates that can feed an integer conditional move.
|
||||
|
||||
@ -15,10 +15,13 @@ define i64 @select_fcmp_false_cmov(double %a, double %b, i64 %c, i64 %d) {
|
||||
define i64 @select_fcmp_oeq_cmov(double %a, double %b, i64 %c, i64 %d) {
|
||||
; CHECK-LABEL: select_fcmp_oeq_cmov
|
||||
; CHECK: ucomisd %xmm1, %xmm0
|
||||
; CHECK-NEXT: setnp %al
|
||||
; CHECK-NEXT: sete %cl
|
||||
; CHECK-NEXT: testb %al, %cl
|
||||
; CHECK-NEXT: cmoveq %rsi, %rdi
|
||||
; SDAG-NEXT: cmovneq %rsi, %rdi
|
||||
; SDAG-NEXT: cmovpq %rsi, %rdi
|
||||
; SDAG-NEXT: movq %rdi, %rax
|
||||
; FAST-NEXT: setnp %al
|
||||
; FAST-NEXT: sete %cl
|
||||
; FAST-NEXT: testb %al, %cl
|
||||
; FAST-NEXT: cmoveq %rsi, %rdi
|
||||
%1 = fcmp oeq double %a, %b
|
||||
%2 = select i1 %1, i64 %c, i64 %d
|
||||
ret i64 %2
|
||||
@ -135,10 +138,13 @@ define i64 @select_fcmp_ule_cmov(double %a, double %b, i64 %c, i64 %d) {
|
||||
define i64 @select_fcmp_une_cmov(double %a, double %b, i64 %c, i64 %d) {
|
||||
; CHECK-LABEL: select_fcmp_une_cmov
|
||||
; CHECK: ucomisd %xmm1, %xmm0
|
||||
; CHECK-NEXT: setp %al
|
||||
; CHECK-NEXT: setne %cl
|
||||
; CHECK-NEXT: orb %al, %cl
|
||||
; CHECK-NEXT: cmoveq %rsi, %rdi
|
||||
; SDAG-NEXT: cmovneq %rdi, %rsi
|
||||
; SDAG-NEXT: cmovpq %rdi, %rsi
|
||||
; SDAG-NEXT: movq %rsi, %rax
|
||||
; FAST-NEXT: setp %al
|
||||
; FAST-NEXT: setne %cl
|
||||
; FAST-NEXT: orb %al, %cl
|
||||
; FAST-NEXT: cmoveq %rsi, %rdi
|
||||
%1 = fcmp une double %a, %b
|
||||
%2 = select i1 %1, i64 %c, i64 %d
|
||||
ret i64 %2
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user