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https://github.com/c64scene-ar/llvm-6502.git
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Add several things.
loads branches setcc working calls Global address External addresses now I can manage malloc calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23887 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
2a2de66db2
commit
8b7f14e970
@ -109,11 +109,74 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
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case ISD::CALL: return SelectCALL(Op);
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case ISD::DYNAMIC_STACKALLOC:
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case ISD::ADD_PARTS:
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case ISD::SUB_PARTS:
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case ISD::SETCC:
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assert(0 && "You want these too?");
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case ISD::SETCC: {
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ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
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assert(MVT::isInteger(N->getOperand(0).getValueType()) && "FP numbers are unnecessary");
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SDOperand Op1 = Select(N->getOperand(0));
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SDOperand Op2 = Select(N->getOperand(1));
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unsigned Opc = Alpha::WTF;
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int dir;
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switch (CC) {
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default: N->dump(); assert(0 && "Unknown integer comparison!");
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case ISD::SETEQ: Opc = Alpha::CMPEQ; dir=1; break;
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case ISD::SETLT: Opc = Alpha::CMPLT; dir = 1; break;
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case ISD::SETLE: Opc = Alpha::CMPLE; dir = 1; break;
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case ISD::SETGT: Opc = Alpha::CMPLT; dir = 0; break;
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case ISD::SETGE: Opc = Alpha::CMPLE; dir = 0; break;
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case ISD::SETULT: Opc = Alpha::CMPULT; dir = 1; break;
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case ISD::SETUGT: Opc = Alpha::CMPULT; dir = 0; break;
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case ISD::SETULE: Opc = Alpha::CMPULE; dir = 1; break;
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case ISD::SETUGE: Opc = Alpha::CMPULE; dir = 0; break;
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case ISD::SETNE: {//Handle this one special
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SDOperand Tmp = CurDAG->getTargetNode(Alpha::CMPEQ, MVT::i64, Op1, Op2);
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CurDAG->SelectNodeTo(N, Alpha::CMPEQ, MVT::i64, CurDAG->getRegister(Alpha::R31, MVT::i64), Tmp);
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return SDOperand(N, 0);
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}
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}
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CurDAG->SelectNodeTo(N, Opc, MVT::i64, dir ? Op1 : Op2, dir ? Op2 : Op1);
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return SDOperand(N, 0);
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}
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case ISD::BRCOND: {
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SDOperand Chain = Select(N->getOperand(0));
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SDOperand CC = Select(N->getOperand(1));
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CurDAG->SelectNodeTo(N, Alpha::BNE, MVT::Other, CC, Chain);
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return SDOperand(N, 0);
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}
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case ISD::LOAD:
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case ISD::EXTLOAD:
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case ISD::ZEXTLOAD:
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case ISD::SEXTLOAD: {
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SDOperand Chain = Select(N->getOperand(0));
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SDOperand Address = Select(N->getOperand(1));
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unsigned opcode = N->getOpcode();
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unsigned Opc = Alpha::WTF;
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if (opcode == ISD::LOAD)
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switch (N->getValueType(0)) {
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default: N->dump(); assert(0 && "Bad load!");
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case MVT::i64: Opc = Alpha::LDQ; break;
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case MVT::f64: Opc = Alpha::LDT; break;
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case MVT::f32: Opc = Alpha::LDS; break;
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}
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else
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switch (cast<VTSDNode>(N->getOperand(3))->getVT()) {
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default: N->dump(); assert(0 && "Bad sign extend!");
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case MVT::i32: Opc = Alpha::LDL;
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assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
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case MVT::i16: Opc = Alpha::LDWU;
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assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
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case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
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case MVT::i8: Opc = Alpha::LDBU;
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assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
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}
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CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
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getI64Imm(0), Address, Chain);
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return SDOperand(N, Op.ResNo);
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}
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case ISD::BR: {
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CurDAG->SelectNodeTo(N, Alpha::BR_DAG, MVT::Other, N->getOperand(1),
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Select(N->getOperand(0)));
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@ -185,6 +248,11 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
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CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64, GA, getGlobalBaseReg());
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return SDOperand(N, 0);
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}
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case ISD::ExternalSymbol:
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CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64,
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CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(), MVT::i64),
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CurDAG->getRegister(AlphaLowering.getVRegGP(), MVT::i64));
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return SDOperand(N, 0);
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case ISD::CALLSEQ_START:
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case ISD::CALLSEQ_END: {
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@ -222,44 +290,37 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
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SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
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SDNode *N = Op.Val;
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SDOperand Chain = Select(N->getOperand(0));
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SDOperand InFlag; // Null incoming flag value.
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SDOperand Addr = Select(N->getOperand(1));
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// unsigned CallOpcode;
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std::vector<SDOperand> CallOperands;
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std::vector<MVT::ValueType> TypeOperands;
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CallOperands.push_back(CurDAG->getCopyToReg(Chain, Alpha::R27, Addr));
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CallOperands.push_back(getI64Imm(0));
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//grab the arguments
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for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
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CallOperands.push_back(Select(N->getOperand(i)));
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TypeOperands.push_back(N->getOperand(i).getValueType());
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CallOperands.push_back(Select(N->getOperand(i)));
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}
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int count = N->getNumOperands() - 2;
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static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
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Alpha::R19, Alpha::R20, Alpha::R21};
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static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
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Alpha::F19, Alpha::F20, Alpha::F21};
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for (unsigned i = 0; i < std::min((size_t)6, CallOperands.size()); ++i) {
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for (int i = 0; i < std::min(6, count); ++i) {
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if (MVT::isInteger(TypeOperands[i])) {
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Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
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InFlag = Chain.getValue(1);
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CallOperands.push_back(CurDAG->getRegister(args_int[i], TypeOperands[i]));
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Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i]);
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} else {
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assert(0 && "No FP support yet");
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assert(0 && "No FP support yet");
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}
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}
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assert(CallOperands.size() <= 6 && "Too big a call");
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Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr);
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// Finally, once everything is in registers to pass to the call, emit the
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// call itself.
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if (InFlag.Val)
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CallOperands.push_back(InFlag); // Strong dep on register copies.
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else
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CallOperands.push_back(Chain); // Weak dep on whatever occurs before
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Chain = CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag, CallOperands);
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Chain = CurDAG->getTargetNode(Alpha::JSRDAG, MVT::Other, Chain );
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std::vector<SDOperand> CallResults;
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@ -267,8 +328,7 @@ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
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default: assert(0 && "Unexpected ret value!");
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case MVT::Other: break;
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case MVT::i64:
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Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64,
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Chain.getValue(1)).getValue(1);
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Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64).getValue(1);
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CallResults.push_back(Chain.getValue(0));
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break;
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}
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@ -55,7 +55,7 @@ def immZAP : PatLeaf<(imm), [{
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UImm >>= 8;
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}
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return build != 0;
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}]>;
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}], iZAPX>;
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def intop : PatFrag<(ops node:$op), (sext_inreg node:$op, i32)>;
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@ -311,8 +311,8 @@ def ZAP : OForm< 0x12, 0x30, "zap $RA,$RB,$RC", []>; //Zero bytes
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def ZAPi : OFormL<0x12, 0x30, "zap $RA,$L,$RC", []>; //Zero bytes
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//FIXME: what to do about zapnot? see ZAP :)
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def ZAPNOT : OForm< 0x12, 0x31, "zapnot $RA,$RB,$RC", []>; //Zero bytes not
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def ZAPNOTi : OFormL<0x12, 0x31, "zapnot $RA,$L,$RC", []>;
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def : Pat<(and GPRC:$OP1, immZAP:$OP2), (ZAPNOTi GPRC:$OP1, (iZAPX immZAP:$OP2))>;
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def ZAPNOTi : OFormL<0x12, 0x31, "zapnot $RA,$L,$RC",
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[(set GPRC:$RC, (and GPRC:$RA, immZAP:$L))]>;
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//Comparison, int
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def CMPBGE : OForm< 0x10, 0x0F, "cmpbge $RA,$RB,$RC", []>; //Compare byte
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@ -367,6 +367,14 @@ let isCall = 1,
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def JSR : MbrForm< 0x1A, 0x01, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to subroutine
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def BSR : BForm<0x34, "bsr $RA,$DISP">; //Branch to subroutine
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}
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let isCall = 1,
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Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
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R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
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F0, F1,
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F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
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F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R27, R29] in {
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def JSRDAG : MbrForm< 0x1A, 0x01, (ops ), "jsr $$26,($$27),0">; //Jump to subroutine
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}
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let isCall = 1, Defs = [R24, R25, R27, R28], Uses = [R24, R25] in
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def JSRs : MbrForm< 0x1A, 0x01, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to div or rem
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