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Remove and simplify some more machineinstr/machineoperand stuff.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28105 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-05-04 18:16:01 +00:00
parent 2d90ac7ca6
commit 8b915b4ed2
7 changed files with 28 additions and 62 deletions
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30
include/llvm/CodeGen/MachineInstr.h
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@ -261,23 +261,8 @@ public:
//===----------------------------------------------------------------------===//
// class MachineInstr
//
// Purpose:
// Representation of each machine instruction.
//
// MachineOpCode must be an enum, defined separately for each target.
// E.g., It is defined in SparcInstructionSelection.h for the SPARC.
//
// There are 2 kinds of operands:
//
// (1) Explicit operands of the machine instruction in vector operands[]
//
// (2) "Implicit operands" are values implicitly used or defined by the
// machine instruction, such as arguments to a CALL, return value of
// a CALL (if any), and return value of a RETURN.
//===----------------------------------------------------------------------===//
/// MachineInstr - Representation of each machine instruction.
///
class MachineInstr {
short Opcode; // the opcode
std::vector<MachineOperand> operands; // the operands
@ -287,9 +272,7 @@ class MachineInstr {
// OperandComplete - Return true if it's illegal to add a new operand
bool OperandsComplete() const;
//Constructor used by clone() method
MachineInstr(const MachineInstr&);
void operator=(const MachineInstr&); // DO NOT IMPLEMENT
// Intrusive list support
@ -297,12 +280,9 @@ class MachineInstr {
friend struct ilist_traits<MachineInstr>;
public:
/// MachineInstr ctor - This constructor only does a _reserve_ of the
/// operands, not a resize for them. It is expected that if you use this that
/// you call add* methods below to fill up the operands, instead of the Set
/// methods. Eventually, the "resizing" ctors will be phased out.
///
MachineInstr(short Opcode, unsigned numOperands, bool XX, bool YY);
/// MachineInstr ctor - This constructor reserve's space for numOperand
/// operands.
MachineInstr(short Opcode, unsigned numOperands);
/// MachineInstr ctor - Work exactly the same as the ctor above, except that
/// the MachineInstr is created and added to the end of the specified basic

24
include/llvm/CodeGen/MachineInstrBuilder.h
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@ -47,20 +47,6 @@ public:
return *this;
}
/// addZImm - Add a new zero extended immediate operand...
///
const MachineInstrBuilder &addZImm(unsigned Val) const {
MI->addImmOperand(Val);
return *this;
}
/// addImm64 - Add a new 64-bit immediate operand...
///
const MachineInstrBuilder &addImm64(uint64_t Val) const {
MI->addImmOperand(Val);
return *this;
}
const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB) const {
MI->addMachineBasicBlockOperand(MBB);
return *this;
@ -99,7 +85,7 @@ public:
/// allow for memory efficient representation of machine instructions.
///
inline MachineInstrBuilder BuildMI(int Opcode, unsigned NumOperands) {
return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands, true, true));
return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands));
}
/// BuildMI - This version of the builder sets up the first operand as a
@ -110,8 +96,8 @@ inline MachineInstrBuilder BuildMI(
int Opcode, unsigned NumOperands,
unsigned DestReg,
MachineOperand::UseType useType = MachineOperand::Def) {
return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands+1,
true, true)).addReg(DestReg, useType);
return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands+1))
.addReg(DestReg, useType);
}
/// BuildMI - This version of the builder inserts the newly-built
@ -124,7 +110,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
MachineBasicBlock::iterator I,
int Opcode, unsigned NumOperands,
unsigned DestReg) {
MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1);
BB.insert(I, MI);
return MachineInstrBuilder(MI).addReg(DestReg, MachineOperand::Def);
}
@ -136,7 +122,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
MachineBasicBlock::iterator I,
int Opcode, unsigned NumOperands) {
MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
MachineInstr *MI = new MachineInstr(Opcode, NumOperands);
BB.insert(I, MI);
return MachineInstrBuilder(MI);
}

2
lib/CodeGen/MachineBasicBlock.cpp
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@ -47,7 +47,7 @@ void ilist_traits<MachineBasicBlock>::removeNodeFromList(MachineBasicBlock* N) {
MachineInstr* ilist_traits<MachineInstr>::createSentinel() {
MachineInstr* dummy = new MachineInstr(0, 0, true, true);
MachineInstr* dummy = new MachineInstr(0, 0);
LeakDetector::removeGarbageObject(dummy);
return dummy;
}

2
lib/CodeGen/MachineInstr.cpp
View File

@ -41,7 +41,7 @@ namespace llvm {
/// add* methods below to fill up the operands, instead of the Set methods.
/// Eventually, the "resizing" ctors will be phased out.
///
MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY)
MachineInstr::MachineInstr(short opcode, unsigned numOperands)
: Opcode(opcode), parent(0) {
operands.reserve(numOperands);
// Make sure that we get added to a machine basicblock

2
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -184,7 +184,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
#endif
// Create the new machine instruction.
MachineInstr *MI = new MachineInstr(Opc, NumMIOperands, true, true);
MachineInstr *MI = new MachineInstr(Opc, NumMIOperands);
// Add result register values for things that are defined by this
// instruction.

12
lib/Target/X86/X86InstrBuilder.h
View File

@ -61,7 +61,7 @@ inline const MachineInstrBuilder &addDirectMem(const MachineInstrBuilder &MIB,
unsigned Reg) {
// Because memory references are always represented with four
// values, this adds: Reg, [1, NoReg, 0] to the instruction.
return MIB.addReg(Reg).addZImm(1).addReg(0).addImm(0);
return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0);
}
@ -71,14 +71,14 @@ inline const MachineInstrBuilder &addDirectMem(const MachineInstrBuilder &MIB,
///
inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB,
unsigned Reg, int Offset) {
return MIB.addReg(Reg).addZImm(1).addReg(0).addImm(Offset);
return MIB.addReg(Reg).addImm(1).addReg(0).addImm(Offset);
}
/// addRegReg - This function is used to add a memory reference of the form:
/// [Reg + Reg].
inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
unsigned Reg1, unsigned Reg2) {
return MIB.addReg(Reg1).addZImm(1).addReg(Reg2).addImm(0);
return MIB.addReg(Reg1).addImm(1).addReg(Reg2).addImm(0);
}
inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
@ -91,7 +91,7 @@ inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
MIB.addFrameIndex(AM.Base.FrameIndex);
else
assert (0);
MIB.addZImm(AM.Scale).addReg(AM.IndexReg);
MIB.addImm(AM.Scale).addReg(AM.IndexReg);
if (AM.GV)
return MIB.addGlobalAddress(AM.GV, AM.Disp);
else
@ -105,7 +105,7 @@ inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
///
inline const MachineInstrBuilder &
addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
return MIB.addFrameIndex(FI).addZImm(1).addReg(0).addImm(Offset);
return MIB.addFrameIndex(FI).addImm(1).addReg(0).addImm(Offset);
}
/// addConstantPoolReference - This function is used to add a reference to the
@ -117,7 +117,7 @@ addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
inline const MachineInstrBuilder &
addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
int Offset = 0) {
return MIB.addConstantPoolIndex(CPI).addZImm(1).addReg(0).addImm(Offset);
return MIB.addConstantPoolIndex(CPI).addImm(1).addReg(0).addImm(Offset);
}
} // End llvm namespace

18
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -139,14 +139,14 @@ static MachineInstr *MakeMRIInst(unsigned Opcode, unsigned FrameIndex,
MachineInstr *MI) {
return addFrameReference(BuildMI(Opcode, 6), FrameIndex)
.addReg(MI->getOperand(1).getReg())
.addZImm(MI->getOperand(2).getImmedValue());
.addImm(MI->getOperand(2).getImmedValue());
}
static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
MachineInstr *MI) {
if (MI->getOperand(1).isImmediate())
return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
.addZImm(MI->getOperand(1).getImmedValue());
.addImm(MI->getOperand(1).getImmedValue());
else if (MI->getOperand(1).isGlobalAddress())
return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
.addGlobalAddress(MI->getOperand(1).getGlobal(),
@ -160,7 +160,7 @@ static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
static MachineInstr *MakeM0Inst(unsigned Opcode, unsigned FrameIndex,
MachineInstr *MI) {
return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addZImm(0);
return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addImm(0);
}
static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
@ -174,7 +174,7 @@ static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex,
MachineInstr *MI) {
const MachineOperand& op = MI->getOperand(0);
return addFrameReference(BuildMI(Opcode, 6, op.getReg(), op.getUseType()),
FrameIndex).addZImm(MI->getOperand(2).getImmedValue());
FrameIndex).addImm(MI->getOperand(2).getImmedValue());
}
@ -620,7 +620,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineInstr *New = 0;
if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
.addZImm(Amount);
.addImm(Amount);
} else {
assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
// factor out the amount the callee already popped.
@ -629,7 +629,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
if (Amount) {
unsigned Opc = Amount < 128 ? X86::ADD32ri8 : X86::ADD32ri;
New = BuildMI(Opc, 1, X86::ESP,
MachineOperand::UseAndDef).addZImm(Amount);
MachineOperand::UseAndDef).addImm(Amount);
}
}
@ -644,7 +644,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
unsigned Opc = CalleeAmt < 128 ? X86::SUB32ri8 : X86::SUB32ri;
MachineInstr *New =
BuildMI(Opc, 1, X86::ESP,
MachineOperand::UseAndDef).addZImm(CalleeAmt);
MachineOperand::UseAndDef).addImm(CalleeAmt);
MBB.insert(I, New);
}
}
@ -793,11 +793,11 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
if (NumBytes > 0) {
unsigned Opc = NumBytes < 128 ? X86::ADD32ri8 : X86::ADD32ri;
BuildMI(MBB, MBBI, Opc, 2)
.addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(NumBytes);
.addReg(X86::ESP, MachineOperand::UseAndDef).addImm(NumBytes);
} else if ((int)NumBytes < 0) {
unsigned Opc = -NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri;
BuildMI(MBB, MBBI, Opc, 2)
.addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(-NumBytes);
.addReg(X86::ESP, MachineOperand::UseAndDef).addImm(-NumBytes);
}
}
}