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https://github.com/c64scene-ar/llvm-6502.git
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[Hexagon] Add New TSFlags to be used in the upcoming patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208239 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jyotsna Verma
parent
4842e7db63
commit
8b915bad69
@ -8,7 +8,7 @@
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Hexagon Intruction Flags +
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// Hexagon Instruction Flags +
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//
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// *** Must match HexagonBaseInfo.h ***
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//===----------------------------------------------------------------------===//
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@ -68,7 +68,7 @@ def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
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//===----------------------------------------------------------------------===//
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// Intruction Class Declaration +
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// Instruction Class Declaration +
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//===----------------------------------------------------------------------===//
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class OpcodeHexagon {
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@ -104,54 +104,72 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
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// Solo instructions, i.e., those that cannot be in a packet with others.
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bits<1> isSolo = 0;
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let TSFlags{5} = isSolo;
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// Packed only with A or X-type instructions.
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bits<1> isSoloAX = 0;
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let TSFlags{6} = isSoloAX;
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// Only A-type instruction in first slot or nothing.
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bits<1> isSoloAin1 = 0;
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let TSFlags{7} = isSoloAin1;
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// Predicated instructions.
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bits<1> isPredicated = 0;
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let TSFlags{6} = isPredicated;
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let TSFlags{8} = isPredicated;
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bits<1> isPredicatedFalse = 0;
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let TSFlags{7} = isPredicatedFalse;
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let TSFlags{9} = isPredicatedFalse;
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bits<1> isPredicatedNew = 0;
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let TSFlags{8} = isPredicatedNew;
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let TSFlags{10} = isPredicatedNew;
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bits<1> isPredicateLate = 0;
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let TSFlags{11} = isPredicateLate; // Late predicate producer insn.
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// New-value insn helper fields.
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bits<1> isNewValue = 0;
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let TSFlags{9} = isNewValue; // New-value consumer insn.
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let TSFlags{12} = isNewValue; // New-value consumer insn.
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bits<1> hasNewValue = 0;
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let TSFlags{10} = hasNewValue; // New-value producer insn.
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let TSFlags{13} = hasNewValue; // New-value producer insn.
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bits<3> opNewValue = 0;
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let TSFlags{13-11} = opNewValue; // New-value produced operand.
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bits<2> opNewBits = 0;
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let TSFlags{15-14} = opNewBits; // New-value opcode bits location: 0, 8, 16.
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let TSFlags{16-14} = opNewValue; // New-value produced operand.
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bits<1> isNVStorable = 0;
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let TSFlags{16} = isNVStorable; // Store that can become new-value store.
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let TSFlags{17} = isNVStorable; // Store that can become new-value store.
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bits<1> isNVStore = 0;
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let TSFlags{17} = isNVStore; // New-value store insn.
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let TSFlags{18} = isNVStore; // New-value store insn.
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bits<1> isCVLoadable = 0;
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let TSFlags{19} = isCVLoadable; // Load that can become cur-value load.
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bits<1> isCVLoad = 0;
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let TSFlags{20} = isCVLoad; // Cur-value load insn.
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// Immediate extender helper fields.
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bits<1> isExtendable = 0;
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let TSFlags{18} = isExtendable; // Insn may be extended.
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let TSFlags{21} = isExtendable; // Insn may be extended.
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bits<1> isExtended = 0;
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let TSFlags{19} = isExtended; // Insn must be extended.
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let TSFlags{22} = isExtended; // Insn must be extended.
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bits<3> opExtendable = 0;
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let TSFlags{22-20} = opExtendable; // Which operand may be extended.
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let TSFlags{25-23} = opExtendable; // Which operand may be extended.
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bits<1> isExtentSigned = 0;
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let TSFlags{23} = isExtentSigned; // Signed or unsigned range.
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let TSFlags{26} = isExtentSigned; // Signed or unsigned range.
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bits<5> opExtentBits = 0;
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let TSFlags{28-24} = opExtentBits; //Number of bits of range before extending.
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let TSFlags{31-27} = opExtentBits; //Number of bits of range before extending.
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bits<2> opExtentAlign = 0;
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let TSFlags{33-32} = opExtentAlign; // Alignment exponent before extending.
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// If an instruction is valid on a subtarget (v2-v5), set the corresponding
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// bit from validSubTargets. v2 is the least significant bit.
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// By default, instruction is valid on all subtargets.
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SubTarget validSubTargets = HasV2SubT;
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let TSFlags{32-29} = validSubTargets.Value;
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let TSFlags{37-34} = validSubTargets.Value;
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// Addressing mode for load/store instructions.
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AddrModeType addrMode = NoAddrMode;
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let TSFlags{35-33} = addrMode.Value;
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let TSFlags{42-40} = addrMode.Value;
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// Memory access size for mem access instructions (load/store)
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MemAccessSize accessSize = NoMemAccess;
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let TSFlags{38-36} = accessSize.Value;
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let TSFlags{45-43} = accessSize.Value;
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bits<1> isTaken = 0;
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let TSFlags {47} = isTaken; // Branch prediction.
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bits<1> isFP = 0;
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let TSFlags {48} = isFP; // Floating-point.
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// Fields used for relation models.
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string BaseOpcode = "";
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@ -173,7 +191,7 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
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}
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//===----------------------------------------------------------------------===//
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// Intruction Classes Definitions +
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// Instruction Classes Definitions +
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//===----------------------------------------------------------------------===//
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// LD Instruction Class in V2/V3/V4.
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@ -317,7 +335,7 @@ class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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: InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>;
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//===----------------------------------------------------------------------===//
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// Intruction Classes Definitions -
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// Instruction Classes Definitions -
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//===----------------------------------------------------------------------===//
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@ -768,12 +768,13 @@ class T_JMP <dag InsDag, list<dag> JumpList = []>
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let InputType = "imm", isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
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Defs = [PC], isPredicated = 1, opExtentBits = 17 in
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class T_JMP_c <bit PredNot, bit isPredNew, bit isTaken>:
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class T_JMP_c <bit PredNot, bit isPredNew, bit isTak>:
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JInst<(outs ), (ins PredRegs:$src, brtarget:$dst),
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!if(PredNot, "if (!$src", "if ($src")#
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!if(isPredNew, ".new) ", ") ")#"jump"#
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!if(isPredNew, !if(isTaken, ":t ", ":nt "), " ")#"$dst"> {
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!if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> {
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let isTaken = isTak;
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let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), "");
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let isPredicatedFalse = PredNot;
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let isPredicatedNew = isPredNew;
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@ -784,7 +785,7 @@ class T_JMP_c <bit PredNot, bit isPredNew, bit isTaken>:
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let Inst{27-24} = 0b1100;
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let Inst{21} = PredNot;
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let Inst{12} = !if(isPredNew, isTaken, zero);
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let Inst{12} = !if(isPredNew, isTak, zero);
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let Inst{11} = isPredNew;
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let Inst{9-8} = src;
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let Inst{23-22} = dst{16-15};
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@ -806,12 +807,13 @@ class T_JMPr<dag InsDag = (ins IntRegs:$dst)>
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}
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let Defs = [PC], isPredicated = 1, InputType = "reg" in
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class T_JMPr_c <bit PredNot, bit isPredNew, bit isTaken>:
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class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>:
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JRInst <(outs ), (ins PredRegs:$src, IntRegs:$dst),
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!if(PredNot, "if (!$src", "if ($src")#
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!if(isPredNew, ".new) ", ") ")#"jumpr"#
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!if(isPredNew, !if(isTaken, ":t ", ":nt "), " ")#"$dst"> {
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!if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> {
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let isTaken = isTak;
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let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), "");
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let isPredicatedFalse = PredNot;
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let isPredicatedNew = isPredNew;
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@ -823,7 +825,7 @@ class T_JMPr_c <bit PredNot, bit isPredNew, bit isTaken>:
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let Inst{27-22} = 0b001101;
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let Inst{21} = PredNot;
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let Inst{20-16} = dst;
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let Inst{12} = !if(isPredNew, isTaken, zero);
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let Inst{12} = !if(isPredNew, isTak, zero);
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let Inst{11} = isPredNew;
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let Inst{9-8} = src;
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let Predicates = !if(isPredNew, [HasV3T], [HasV2T]);
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@ -1004,13 +1004,13 @@ defm POST_STwri: ST_PostInc_nv <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in
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class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
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bit isNegCond, bit isTaken>
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bit isNegCond, bit isTak>
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: NVInst_V4<(outs),
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(ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
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"if ("#!if(isNegCond, "!","")#mnemonic#
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"($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
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"$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
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#!if(isTaken, "t","nt")#" $offset",
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#!if(isTak, "t","nt")#" $offset",
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[]>, Requires<[HasV4T]> {
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bits<5> src1;
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@ -1019,6 +1019,7 @@ class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
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bits<5> RegOp; // Non-New-Value Operand
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bits<11> offset;
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let isTaken = isTak;
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let isBrTaken = !if(isTaken, "true", "false");
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let isPredicatedFalse = isNegCond;
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@ -1030,7 +1031,7 @@ class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
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let Inst{25-23} = majOp;
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let Inst{22} = isNegCond;
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let Inst{18-16} = Ns;
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let Inst{13} = isTaken;
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let Inst{13} = isTak;
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let Inst{12-8} = RegOp;
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let Inst{21-20} = offset{10-9};
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let Inst{7-1} = offset{8-2};
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@ -1078,13 +1079,14 @@ let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in
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class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
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bit isTaken>
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bit isTak>
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: NVInst_V4<(outs),
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(ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
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"if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
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#!if(isTaken, "t","nt")#" $offset",
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#!if(isTak, "t","nt")#" $offset",
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[]>, Requires<[HasV4T]> {
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let isTaken = isTak;
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let isPredicatedFalse = isNegCond;
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let isBrTaken = !if(isTaken, "true", "false");
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@ -1097,7 +1099,7 @@ class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
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let Inst{25-23} = majOp;
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let Inst{22} = isNegCond;
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let Inst{18-16} = src1;
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let Inst{13} = isTaken;
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let Inst{13} = isTak;
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let Inst{12-8} = src2;
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let Inst{21-20} = offset{10-9};
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let Inst{7-1} = offset{8-2};
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@ -1135,14 +1137,15 @@ let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
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let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11 in
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class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
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bit isNegCond, bit isTaken>
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bit isNegCond, bit isTak>
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: NVInst_V4<(outs),
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(ins IntRegs:$src1, brtarget:$offset),
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"if ("#!if(isNegCond, "!","")#mnemonic
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#"($src1.new, #"#ImmVal#")) jump:"
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#!if(isTaken, "t","nt")#" $offset",
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#!if(isTak, "t","nt")#" $offset",
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[]>, Requires<[HasV4T]> {
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let isTaken = isTak;
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let isPredicatedFalse = isNegCond;
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let isBrTaken = !if(isTaken, "true", "false");
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@ -1153,7 +1156,7 @@ class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
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let Inst{25-23} = majOp;
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let Inst{22} = isNegCond;
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let Inst{18-16} = src1;
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let Inst{13} = isTaken;
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let Inst{13} = isTak;
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let Inst{21-20} = offset{10-9};
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let Inst{7-1} = offset{8-2};
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}
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@ -87,70 +87,82 @@ namespace HexagonII {
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// Solo instructions.
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SoloPos = 5,
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SoloMask = 0x1,
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// Packed only with A or X-type instructions.
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SoloAXPos = 6,
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SoloAXMask = 0x1,
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// Only A-type instruction in first slot or nothing.
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SoloAin1Pos = 7,
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SoloAin1Mask = 0x1,
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// Predicated instructions.
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PredicatedPos = 6,
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PredicatedPos = 8,
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PredicatedMask = 0x1,
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PredicatedFalsePos = 7,
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PredicatedFalsePos = 9,
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PredicatedFalseMask = 0x1,
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PredicatedNewPos = 8,
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PredicatedNewPos = 10,
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PredicatedNewMask = 0x1,
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PredicateLatePos = 11,
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PredicateLateMask = 0x1,
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// New-Value consumer instructions.
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NewValuePos = 9,
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NewValuePos = 12,
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NewValueMask = 0x1,
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// New-Value producer instructions.
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hasNewValuePos = 10,
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hasNewValuePos = 13,
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hasNewValueMask = 0x1,
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// Which operand consumes or produces a new value.
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NewValueOpPos = 11,
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NewValueOpPos = 14,
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NewValueOpMask = 0x7,
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// Which bits encode the new value.
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NewValueBitsPos = 14,
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NewValueBitsMask = 0x3,
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// Stores that can become new-value stores.
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mayNVStorePos = 16,
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mayNVStorePos = 17,
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mayNVStoreMask = 0x1,
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// New-value store instructions.
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NVStorePos = 17,
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NVStorePos = 18,
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NVStoreMask = 0x1,
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// Loads that can become current-value loads.
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mayCVLoadPos = 19,
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mayCVLoadMask = 0x1,
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// Current-value load instructions.
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CVLoadPos = 20,
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CVLoadMask = 0x1,
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// Extendable insns.
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ExtendablePos = 18,
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ExtendablePos = 21,
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ExtendableMask = 0x1,
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// Insns must be extended.
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ExtendedPos = 19,
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ExtendedPos = 22,
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ExtendedMask = 0x1,
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// Which operand may be extended.
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ExtendableOpPos = 20,
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ExtendableOpPos = 23,
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ExtendableOpMask = 0x7,
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// Signed or unsigned range.
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ExtentSignedPos = 23,
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ExtentSignedPos = 26,
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ExtentSignedMask = 0x1,
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// Number of bits of range before extending operand.
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ExtentBitsPos = 24,
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ExtentBitsPos = 27,
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ExtentBitsMask = 0x1f,
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// Alignment power-of-two before extending operand.
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ExtentAlignPos = 32,
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ExtentAlignMask = 0x3,
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// Valid subtargets
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validSubTargetPos = 29,
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validSubTargetPos = 34,
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validSubTargetMask = 0xf,
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// Addressing mode for load/store instructions.
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AddrModePos = 33,
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AddrModePos = 40,
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AddrModeMask = 0x7,
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// Access size for load/store instructions.
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MemAccessSizePos = 43,
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MemAccesSizeMask = 0x7,
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// Access size of memory access instructions (load/store).
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MemAccessSizePos = 36,
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MemAccesSizeMask = 0x7
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// Branch predicted taken.
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TakenPos = 47,
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TakenMask = 0x1,
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// Floating-point instructions.
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FPPos = 48,
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FPMask = 0x1
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};
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// *** The code above must match HexagonInstrFormat*.td *** //
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