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SDAGBuilder: Remove register sets that were never read and prune dead code surrounding it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151364 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -5677,22 +5677,6 @@ public:
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: TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
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}
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/// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
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/// busy in OutputRegs/InputRegs.
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void MarkAllocatedRegs(bool isOutReg, bool isInReg,
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std::set<unsigned> &OutputRegs,
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std::set<unsigned> &InputRegs,
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const TargetRegisterInfo &TRI) const {
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if (isOutReg) {
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for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
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MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
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}
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if (isInReg) {
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for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
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MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
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}
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}
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/// getCallOperandValEVT - Return the EVT of the Value* that this operand
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/// corresponds to. If there is no Value* for this operand, it returns
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/// MVT::Other.
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@ -5740,18 +5724,6 @@ public:
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return TLI.getValueType(OpTy, true);
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}
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private:
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/// MarkRegAndAliases - Mark the specified register and all aliases in the
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/// specified set.
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static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
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const TargetRegisterInfo &TRI) {
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assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
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Regs.insert(Reg);
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if (const unsigned *Aliases = TRI.getAliasSet(Reg))
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for (; *Aliases; ++Aliases)
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Regs.insert(*Aliases);
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}
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};
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typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
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@ -5765,39 +5737,13 @@ typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
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/// allocation. This produces generally horrible, but correct, code.
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///
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/// OpInfo describes the operand.
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/// Input and OutputRegs are the set of already allocated physical registers.
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///
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static void GetRegistersForValue(SelectionDAG &DAG,
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const TargetLowering &TLI,
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DebugLoc DL,
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SDISelAsmOperandInfo &OpInfo,
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std::set<unsigned> &OutputRegs,
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std::set<unsigned> &InputRegs) {
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SDISelAsmOperandInfo &OpInfo) {
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LLVMContext &Context = *DAG.getContext();
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// Compute whether this value requires an input register, an output register,
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// or both.
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bool isOutReg = false;
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bool isInReg = false;
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switch (OpInfo.Type) {
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case InlineAsm::isOutput:
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isOutReg = true;
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// If there is an input constraint that matches this, we need to reserve
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// the input register so no other inputs allocate to it.
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isInReg = OpInfo.hasMatchingInput();
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break;
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case InlineAsm::isInput:
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isInReg = true;
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isOutReg = false;
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break;
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case InlineAsm::isClobber:
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isOutReg = true;
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isInReg = true;
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break;
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}
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MachineFunction &MF = DAG.getMachineFunction();
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SmallVector<unsigned, 4> Regs;
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@ -5871,8 +5817,6 @@ static void GetRegistersForValue(SelectionDAG &DAG,
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}
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OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
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const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
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OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
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return;
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}
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@ -5903,8 +5847,6 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
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/// ConstraintOperands - Information about all of the constraints.
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SDISelAsmOperandInfoVector ConstraintOperands;
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std::set<unsigned> OutputRegs, InputRegs;
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TargetLowering::AsmOperandInfoVector
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TargetConstraints = TLI.ParseConstraints(CS);
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@ -6066,8 +6008,7 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
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// If this constraint is for a specific register, allocate it before
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// anything else.
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if (OpInfo.ConstraintType == TargetLowering::C_Register)
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GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
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InputRegs);
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GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
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}
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// Second pass - Loop over all of the operands, assigning virtual or physregs
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@ -6078,8 +6019,7 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
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// C_Register operands have already been allocated, Other/Memory don't need
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// to be.
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if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
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GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
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InputRegs);
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GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
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}
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// AsmNodeOperands - The operands for the ISD::INLINEASM node.
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