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https://github.com/c64scene-ar/llvm-6502.git
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Refactoring of SSE convert intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106808 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
fe5e4dabbf
commit
8b94297727
@ -624,67 +624,67 @@ defm CVTSI2SS : sse12_cvt<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
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defm CVTSI2SD : sse12_cvt<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
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"cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
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// Match intrinsics which expect XMM operand(s).
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def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
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"cvtss2si\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
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def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
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"cvtss2si\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (int_x86_sse_cvtss2si
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(load addr:$src)))]>;
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def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
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"cvtsd2si\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
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def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
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"cvtsd2si\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (int_x86_sse2_cvtsd2si
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(load addr:$src)))]>;
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// Match intrinsics which expect MM and XMM operand(s).
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def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
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"cvtps2pi\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
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def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
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"cvtps2pi\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst, (int_x86_sse_cvtps2pi
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(load addr:$src)))]>;
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def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
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"cvtpd2pi\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
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def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
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"cvtpd2pi\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst, (int_x86_sse_cvtpd2pi
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(memop addr:$src)))]>;
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// Match intrinsics which expect MM and XMM operand(s).
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def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
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"cvttps2pi\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
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def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
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"cvttps2pi\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst, (int_x86_sse_cvttps2pi
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(load addr:$src)))]>;
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def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
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"cvttpd2pi\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
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def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
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"cvttpd2pi\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst, (int_x86_sse_cvttpd2pi
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(memop addr:$src)))]>;
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let Constraints = "$src1 = $dst" in {
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def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
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"cvtpi2ps\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
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VR64:$src2))]>;
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def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
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"cvtpi2ps\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
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(load addr:$src2)))]>;
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multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
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string asm> {
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def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
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[(set DstRC:$dst, (Int SrcRC:$src))]>;
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def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
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[(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
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}
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// Match intrinsics which expect XMM operand(s).
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defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
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f32mem, load, "cvtss2si\t{$src, $dst|$dst, $src}">, XS;
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defm Int_CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
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f128mem, load, "cvtsd2si\t{$src, $dst|$dst, $src}">, XD;
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multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
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string asm, Domain d> {
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def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
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[(set DstRC:$dst, (Int SrcRC:$src))], d>;
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def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
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[(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>;
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}
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// Match intrinsics which expect MM and XMM operand(s).
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defm Int_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
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f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
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SSEPackedSingle>, TB;
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defm Int_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
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f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
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SSEPackedDouble>, TB, OpSize;
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// Match intrinsics which expect MM and XMM operand(s).
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defm Int_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
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f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
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SSEPackedSingle>, TB;
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defm Int_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
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f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
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SSEPackedDouble>, TB, OpSize;
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multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
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RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
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PatFrag ld_frag, string asm, Domain d> {
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def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
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asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>;
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def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst),
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(ins DstRC:$src1, x86memop:$src2), asm,
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[(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>;
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}
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let Constraints = "$src1 = $dst" in
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defm Int_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
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int_x86_sse_cvtpi2ps,
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i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
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SSEPackedSingle>, TB;
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defm Int_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
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i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
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SSEPackedDouble>, TB, OpSize;
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Compare Instructions
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//===----------------------------------------------------------------------===//
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@ -1577,15 +1577,6 @@ def : Pat<(extloadf32 addr:$src),
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(CVTSS2SDrr (MOVSSrm addr:$src))>,
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Requires<[HasSSE2, OptForSpeed]>;
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// Match intrinsics which expect MM and XMM operand(s).
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def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
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"cvtpi2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
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def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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"cvtpi2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse_cvtpi2pd
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(load addr:$src)))]>;
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// Aliases for intrinsics
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def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
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"cvttsd2si\t{$src, $dst|$dst, $src}",
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