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BBVectorize: Check the input types of shuffles for legality
This fixes a bug where shuffles were being fused such that the resulting input types were not legal on the target. This would occur only when both inputs and dependencies were also foldable operations (such as other shuffles) and there were other connected pairs in the same block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167731 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -483,6 +483,8 @@ namespace {
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if (SelectInst *SI = dyn_cast<SelectInst>(I)) {
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T2 = SI->getCondition()->getType();
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} else if (ShuffleVectorInst *SI = dyn_cast<ShuffleVectorInst>(I)) {
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T2 = SI->getOperand(0)->getType();
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}
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}
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@ -987,10 +989,11 @@ namespace {
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// We don't want to fuse to a type that will be split, even
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// if the two input types will also be split and there is no other
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// associated cost.
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unsigned VParts = VTTI->getNumberOfParts(VT1);
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if (VParts > 1)
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unsigned VParts1 = VTTI->getNumberOfParts(VT1),
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VParts2 = VTTI->getNumberOfParts(VT2);
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if (VParts1 > 1 || VParts2 > 1)
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return false;
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else if (!VParts && VCost == ICost + JCost)
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else if ((!VParts1 || !VParts2) && VCost == ICost + JCost)
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return false;
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CostSavings = ICost + JCost - VCost;
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25
test/Transforms/BBVectorize/X86/sh-types.ll
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25
test/Transforms/BBVectorize/X86/sh-types.ll
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@ -0,0 +1,25 @@
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -bb-vectorize -S | FileCheck %s
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define <4 x float> @test7(<4 x float> %A1, <4 x float> %B1, double %C1, double %C2, double %D1, double %D2) {
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%A2 = shufflevector <4 x float> %A1, <4 x float> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
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%B2 = shufflevector <4 x float> %B1, <4 x float> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
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%X1 = shufflevector <4 x float> %A2, <4 x float> undef, <2 x i32> <i32 0, i32 1>
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%X2 = shufflevector <4 x float> %B2, <4 x float> undef, <2 x i32> <i32 2, i32 3>
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%Y1 = shufflevector <2 x float> %X1, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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%Y2 = shufflevector <2 x float> %X2, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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%M1 = fsub double %C1, %D1
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%M2 = fsub double %C2, %D2
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%N1 = fmul double %M1, %C1
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%N2 = fmul double %M2, %C2
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%Z1 = fadd double %N1, %D1
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%Z2 = fadd double %N2, %D2
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%R = fmul <4 x float> %Y1, %Y2
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ret <4 x float> %R
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; CHECK: @test7
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; CHECK-NOT: <8 x float>
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; CHECK: ret <4 x float>
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}
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