6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 04:30:23 +00:00
Code Issues Projects Releases Wiki Activity

[AArch64] Fix a build_vector pattern match fail

Browse Source 
caused by defect in isBuildVectorAllZeros().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211567 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Qin 2014-06-24 05:37:27 +00:00
parent f36c3de849
commit 8c0787e83a
2 changed files with 35 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -148,32 +148,33 @@ bool ISD::isBuildVectorAllZeros(const SDNode *N) {
if (N->getOpcode() != ISD::BUILD_VECTOR) return false; if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
unsigned i = 0, e = N->getNumOperands(); bool IsAllUndef = true;
for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) {
// Skip over all of the undef values. if (N->getOperand(i).getOpcode() == ISD::UNDEF)
while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
++i; IsAllUndef = false;
// Do not accept an all-undef vector.
if (i == e) return false;
// Do not accept build_vectors that aren't all constants or which have non-0 // Do not accept build_vectors that aren't all constants or which have non-0
// elements. // elements. We have to be a bit careful here, as the type of the constant
// may not be the same as the type of the vector elements due to type
// legalization (the elements are promoted to a legal type for the target
// and a vector of a type may be legal when the base element type is not).
// We only want to check enough bits to cover the vector elements, because
// we care if the resultant vector is all zeros, not whether the individual
// constants are.
SDValue Zero = N->getOperand(i); SDValue Zero = N->getOperand(i);
unsigned EltSize = N->getValueType(0).getVectorElementType().getSizeInBits();
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Zero)) { if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Zero)) {
if (!CN->isNullValue()) if (CN->getAPIntValue().countTrailingZeros() < EltSize)
return false; return false;
} else if (ConstantFPSDNode *CFPN = dyn_cast<ConstantFPSDNode>(Zero)) { } else if (ConstantFPSDNode *CFPN = dyn_cast<ConstantFPSDNode>(Zero)) {
if (!CFPN->getValueAPF().isPosZero()) if (CFPN->getValueAPF().bitcastToAPInt().countTrailingZeros() < EltSize)
return false; return false;
} else } else
return false; return false;
}
// Okay, we have at least one 0 value, check to see if the rest match or are // Do not accept an all-undef vector.
// undefs. if (IsAllUndef)
for (++i; i != e; ++i)
if (N->getOperand(i) != Zero &&
N->getOperand(i).getOpcode() != ISD::UNDEF)
return false; return false;
return true; return true;
} }

10
test/CodeGen/AArch64/arm64-build-vector.ll
View File

@ -33,3 +33,13 @@ define <4 x float> @foo(float %a, float %b, float %c, float %d) nounwind {
%4 = insertelement <4 x float> %3, float %d, i32 3 %4 = insertelement <4 x float> %3, float %d, i32 3
ret <4 x float> %4 ret <4 x float> %4
} }
define <8 x i16> @build_all_zero(<8 x i16> %a) #1 {
; CHECK-LABEL: build_all_zero:
; CHECK: movn w[[GREG:[0-9]+]], #0x517f
; CHECK-NEXT: fmov s[[FREG:[0-9]+]], w[[GREG]]
; CHECK-NEXT: mul.8h v0, v0, v[[FREG]]
%b = add <8 x i16> %a, <i16 -32768, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
%c = mul <8 x i16> %b, <i16 -20864, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
ret <8 x i16> %c
}