mirror of
https://github.com/c64scene-ar/llvm-6502.git
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PTX: Add programmable rounding mode specifier for int <-> fp conversion instrs.
Also take this opportunity to clean up the rounding mode pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140854 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Holewinski
parent
0ad7b6e773
commit
8c1dac54f2
@ -16,6 +16,7 @@
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#include "PTX.h"
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#include "PTXTargetMachine.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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@ -33,12 +34,18 @@ namespace llvm {
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class PTXFPRoundingModePass : public MachineFunctionPass {
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private:
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static char ID;
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typedef std::pair<unsigned, unsigned> RndModeDesc;
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PTXTargetMachine& TargetMachine;
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DenseMap<unsigned, RndModeDesc> Instrs;
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public:
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PTXFPRoundingModePass(PTXTargetMachine &TM, CodeGenOpt::Level OptLevel)
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: MachineFunctionPass(ID),
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TargetMachine(TM) {}
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TargetMachine(TM) {
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initializeMap();
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}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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@ -48,6 +55,7 @@ namespace llvm {
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private:
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void initializeMap();
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void processInstruction(MachineInstr &MI);
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}; // class PTXFPRoundingModePass
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} // namespace llvm
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@ -57,7 +65,6 @@ using namespace llvm;
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char PTXFPRoundingModePass::ID = 0;
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bool PTXFPRoundingModePass::runOnMachineFunction(MachineFunction &MF) {
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// Look at each basic block
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for (MachineFunction::iterator bbi = MF.begin(), bbe = MF.end(); bbi != bbe;
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++bbi) {
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@ -72,79 +79,96 @@ bool PTXFPRoundingModePass::runOnMachineFunction(MachineFunction &MF) {
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return false;
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}
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void PTXFPRoundingModePass::processInstruction(MachineInstr &MI) {
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// If the instruction has a rounding mode set to RndDefault, then assign an
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// appropriate rounding mode based on the target device.
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void PTXFPRoundingModePass::initializeMap() {
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using namespace PTXRoundingMode;
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const PTXSubtarget& ST = TargetMachine.getSubtarget<PTXSubtarget>();
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switch (MI.getOpcode()) {
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case PTX::FADDrr32:
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case PTX::FADDri32:
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case PTX::FADDrr64:
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case PTX::FADDri64:
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case PTX::FSUBrr32:
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case PTX::FSUBri32:
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case PTX::FSUBrr64:
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case PTX::FSUBri64:
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case PTX::FMULrr32:
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case PTX::FMULri32:
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case PTX::FMULrr64:
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case PTX::FMULri64:
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if (MI.getOperand(1).getImm() == PTXRoundingMode::RndDefault) {
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MI.getOperand(1).setImm(PTXRoundingMode::RndNearestEven);
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// Build a map of default rounding mode for all instructions that need a
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// rounding mode.
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Instrs[PTX::FADDrr32] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::FADDri32] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::FADDrr64] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::FADDri64] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::FSUBrr32] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::FSUBri32] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::FSUBrr64] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::FSUBri64] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::FMULrr32] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::FMULri32] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::FMULrr64] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::FMULri64] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::FNEGrr32] = std::make_pair(1U, (unsigned)RndNone);
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Instrs[PTX::FNEGri32] = std::make_pair(1U, (unsigned)RndNone);
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Instrs[PTX::FNEGrr64] = std::make_pair(1U, (unsigned)RndNone);
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Instrs[PTX::FNEGri64] = std::make_pair(1U, (unsigned)RndNone);
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unsigned FDivRndMode = ST.fdivNeedsRoundingMode() ? RndNearestEven : RndNone;
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Instrs[PTX::FDIVrr32] = std::make_pair(1U, FDivRndMode);
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Instrs[PTX::FDIVri32] = std::make_pair(1U, FDivRndMode);
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Instrs[PTX::FDIVrr64] = std::make_pair(1U, FDivRndMode);
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Instrs[PTX::FDIVri64] = std::make_pair(1U, FDivRndMode);
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unsigned FMADRndMode = ST.fmadNeedsRoundingMode() ? RndNearestEven : RndNone;
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Instrs[PTX::FMADrrr32] = std::make_pair(1U, FMADRndMode);
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Instrs[PTX::FMADrri32] = std::make_pair(1U, FMADRndMode);
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Instrs[PTX::FMADrii32] = std::make_pair(1U, FMADRndMode);
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Instrs[PTX::FMADrrr64] = std::make_pair(1U, FMADRndMode);
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Instrs[PTX::FMADrri64] = std::make_pair(1U, FMADRndMode);
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Instrs[PTX::FMADrii64] = std::make_pair(1U, FMADRndMode);
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Instrs[PTX::FSQRTrr32] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::FSQRTri32] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::FSQRTrr64] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::FSQRTri64] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::FSINrr32] = std::make_pair(1U, (unsigned)RndApprox);
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Instrs[PTX::FSINri32] = std::make_pair(1U, (unsigned)RndApprox);
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Instrs[PTX::FSINrr64] = std::make_pair(1U, (unsigned)RndApprox);
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Instrs[PTX::FSINri64] = std::make_pair(1U, (unsigned)RndApprox);
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Instrs[PTX::FCOSrr32] = std::make_pair(1U, (unsigned)RndApprox);
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Instrs[PTX::FCOSri32] = std::make_pair(1U, (unsigned)RndApprox);
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Instrs[PTX::FCOSrr64] = std::make_pair(1U, (unsigned)RndApprox);
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Instrs[PTX::FCOSri64] = std::make_pair(1U, (unsigned)RndApprox);
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Instrs[PTX::CVTu16f32] = std::make_pair(1U, (unsigned)RndTowardsZeroInt);
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Instrs[PTX::CVTs16f32] = std::make_pair(1U, (unsigned)RndTowardsZeroInt);
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Instrs[PTX::CVTu16f64] = std::make_pair(1U, (unsigned)RndTowardsZeroInt);
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Instrs[PTX::CVTs16f64] = std::make_pair(1U, (unsigned)RndTowardsZeroInt);
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Instrs[PTX::CVTu32f32] = std::make_pair(1U, (unsigned)RndTowardsZeroInt);
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Instrs[PTX::CVTs32f32] = std::make_pair(1U, (unsigned)RndTowardsZeroInt);
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Instrs[PTX::CVTu32f64] = std::make_pair(1U, (unsigned)RndTowardsZeroInt);
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Instrs[PTX::CVTs32f64] = std::make_pair(1U, (unsigned)RndTowardsZeroInt);
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Instrs[PTX::CVTu64f32] = std::make_pair(1U, (unsigned)RndTowardsZeroInt);
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Instrs[PTX::CVTs64f32] = std::make_pair(1U, (unsigned)RndTowardsZeroInt);
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Instrs[PTX::CVTu64f64] = std::make_pair(1U, (unsigned)RndTowardsZeroInt);
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Instrs[PTX::CVTs64f64] = std::make_pair(1U, (unsigned)RndTowardsZeroInt);
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Instrs[PTX::CVTf32u16] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::CVTf32s16] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::CVTf32u32] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::CVTf32s32] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::CVTf32u64] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::CVTf32s64] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::CVTf32f64] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::CVTf64u16] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::CVTf64s16] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::CVTf64u32] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::CVTf64s32] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::CVTf64u64] = std::make_pair(1U, (unsigned)RndNearestEven);
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Instrs[PTX::CVTf64s64] = std::make_pair(1U, (unsigned)RndNearestEven);
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}
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void PTXFPRoundingModePass::processInstruction(MachineInstr &MI) {
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// Is this an instruction that needs a rounding mode?
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if (Instrs.count(MI.getOpcode())) {
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const RndModeDesc &Desc = Instrs[MI.getOpcode()];
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// Get the rounding mode operand
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MachineOperand &Op = MI.getOperand(Desc.first);
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// Update the rounding mode if needed
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if (Op.getImm() == PTXRoundingMode::RndDefault) {
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Op.setImm(Desc.second);
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}
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break;
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case PTX::FNEGrr32:
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case PTX::FNEGri32:
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case PTX::FNEGrr64:
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case PTX::FNEGri64:
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if (MI.getOperand(1).getImm() == PTXRoundingMode::RndDefault) {
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MI.getOperand(1).setImm(PTXRoundingMode::RndNone);
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}
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break;
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case PTX::FDIVrr32:
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case PTX::FDIVri32:
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case PTX::FDIVrr64:
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case PTX::FDIVri64:
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if (MI.getOperand(1).getImm() == PTXRoundingMode::RndDefault) {
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if (ST.fdivNeedsRoundingMode())
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MI.getOperand(1).setImm(PTXRoundingMode::RndNearestEven);
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else
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MI.getOperand(1).setImm(PTXRoundingMode::RndNone);
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}
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break;
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case PTX::FMADrrr32:
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case PTX::FMADrri32:
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case PTX::FMADrii32:
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case PTX::FMADrrr64:
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case PTX::FMADrri64:
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case PTX::FMADrii64:
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if (MI.getOperand(1).getImm() == PTXRoundingMode::RndDefault) {
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if (ST.fmadNeedsRoundingMode())
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MI.getOperand(1).setImm(PTXRoundingMode::RndNearestEven);
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else
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MI.getOperand(1).setImm(PTXRoundingMode::RndNone);
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}
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break;
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case PTX::FSQRTrr32:
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case PTX::FSQRTri32:
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case PTX::FSQRTrr64:
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case PTX::FSQRTri64:
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if (MI.getOperand(1).getImm() == PTXRoundingMode::RndDefault) {
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MI.getOperand(1).setImm(PTXRoundingMode::RndNearestEven);
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}
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break;
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case PTX::FSINrr32:
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case PTX::FSINri32:
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case PTX::FSINrr64:
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case PTX::FSINri64:
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case PTX::FCOSrr32:
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case PTX::FCOSri32:
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case PTX::FCOSrr64:
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case PTX::FCOSri64:
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if (MI.getOperand(1).getImm() == PTXRoundingMode::RndDefault) {
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MI.getOperand(1).setImm(PTXRoundingMode::RndApprox);
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}
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break;
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}
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}
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@ -655,7 +655,8 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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// PTX cvt instructions
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// Note all of these may actually be used, we just define all possible patterns
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// here.
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// here (that make sense).
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// FIXME: Can we collapse this somehow into a multiclass def?
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// To i16
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def CVTu16u32
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@ -663,13 +664,17 @@ def CVTu16u32
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def CVTu16u64
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: InstPTX<(outs RegI16:$d), (ins RegI64:$a), "cvt.u16.u64\t$d, $a", []>;
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def CVTu16f32
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: InstPTX<(outs RegI16:$d), (ins RegF32:$a), "cvt.rzi.u16.f32\t$d, $a", []>;
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: InstPTX<(outs RegI16:$d), (ins RndMode:$r, RegF32:$a),
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"cvt$r.u16.f32\t$d, $a", []>;
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def CVTs16f32
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: InstPTX<(outs RegI16:$d), (ins RegF32:$a), "cvt.rzi.s16.f32\t$d, $a", []>;
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: InstPTX<(outs RegI16:$d), (ins RndMode:$r, RegF32:$a),
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"cvt$r.s16.f32\t$d, $a", []>;
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def CVTu16f64
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: InstPTX<(outs RegI16:$d), (ins RegF64:$a), "cvt.rzi.u16.f64\t$d, $a", []>;
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: InstPTX<(outs RegI16:$d), (ins RndMode:$r, RegF64:$a),
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"cvt$r.u16.f64\t$d, $a", []>;
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def CVTs16f64
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: InstPTX<(outs RegI16:$d), (ins RegF64:$a), "cvt.rzi.s16.f64\t$d, $a", []>;
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: InstPTX<(outs RegI16:$d), (ins RndMode:$r, RegF64:$a),
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"cvt$r.s16.f64\t$d, $a", []>;
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// To i32
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def CVTu32u16
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@ -679,13 +684,17 @@ def CVTs32s16
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def CVTu32u64
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: InstPTX<(outs RegI32:$d), (ins RegI64:$a), "cvt.u32.u64\t$d, $a", []>;
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def CVTu32f32
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: InstPTX<(outs RegI32:$d), (ins RegF32:$a), "cvt.rzi.u32.f32\t$d, $a", []>;
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: InstPTX<(outs RegI32:$d), (ins RndMode:$r, RegF32:$a),
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"cvt$r.u32.f32\t$d, $a", []>;
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def CVTs32f32
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: InstPTX<(outs RegI32:$d), (ins RegF32:$a), "cvt.rzi.s32.f32\t$d, $a", []>;
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: InstPTX<(outs RegI32:$d), (ins RndMode:$r, RegF32:$a),
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"cvt$r.s32.f32\t$d, $a", []>;
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def CVTu32f64
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: InstPTX<(outs RegI32:$d), (ins RegF64:$a), "cvt.rzi.u32.f64\t$d, $a", []>;
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: InstPTX<(outs RegI32:$d), (ins RndMode:$r, RegF64:$a),
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"cvt$r.u32.f64\t$d, $a", []>;
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def CVTs32f64
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: InstPTX<(outs RegI32:$d), (ins RegF64:$a), "cvt.rzi.s32.f64\t$d, $a", []>;
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: InstPTX<(outs RegI32:$d), (ins RndMode:$r, RegF64:$a),
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"cvt$r.s32.f64\t$d, $a", []>;
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// To i64
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def CVTu64u16
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@ -697,43 +706,60 @@ def CVTu64u32
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def CVTs64s32
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: InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.s64.s32\t$d, $a", []>;
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def CVTu64f32
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: InstPTX<(outs RegI64:$d), (ins RegF32:$a), "cvt.rzi.u64.f32\t$d, $a", []>;
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: InstPTX<(outs RegI64:$d), (ins RndMode:$r, RegF32:$a),
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"cvt$r.u64.f32\t$d, $a", []>;
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def CVTs64f32
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: InstPTX<(outs RegI64:$d), (ins RegF32:$a), "cvt.rzi.s64.f32\t$d, $a", []>;
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: InstPTX<(outs RegI64:$d), (ins RndMode:$r, RegF32:$a),
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"cvt$r.s64.f32\t$d, $a", []>;
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def CVTu64f64
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: InstPTX<(outs RegI64:$d), (ins RegF64:$a), "cvt.rzi.u64.f64\t$d, $a", []>;
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: InstPTX<(outs RegI64:$d), (ins RndMode:$r, RegF64:$a),
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"cvt$r.u64.f64\t$d, $a", []>;
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def CVTs64f64
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: InstPTX<(outs RegI64:$d), (ins RegF64:$a), "cvt.rzi.s64.f64\t$d, $a", []>;
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: InstPTX<(outs RegI64:$d), (ins RndMode:$r, RegF64:$a),
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"cvt$r.s64.f64\t$d, $a", []>;
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// To f32
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def CVTf32u16
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: InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.u16\t$d, $a", []>;
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: InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegI16:$a),
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"cvt$r.f32.u16\t$d, $a", []>;
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def CVTf32s16
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: InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.s16\t$d, $a", []>;
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: InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegI16:$a),
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"cvt$r.f32.s16\t$d, $a", []>;
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def CVTf32u32
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: InstPTX<(outs RegF32:$d), (ins RegI32:$a), "cvt.rn.f32.u32\t$d, $a", []>;
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: InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegI32:$a),
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"cvt$r.f32.u32\t$d, $a", []>;
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def CVTf32s32
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: InstPTX<(outs RegF32:$d), (ins RegI32:$a), "cvt.rn.f32.s32\t$d, $a", []>;
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: InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegI32:$a),
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"cvt$r.f32.s32\t$d, $a", []>;
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def CVTf32u64
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: InstPTX<(outs RegF32:$d), (ins RegI64:$a), "cvt.rn.f32.u64\t$d, $a", []>;
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: InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegI64:$a),
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"cvt$r.f32.u64\t$d, $a", []>;
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def CVTf32s64
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: InstPTX<(outs RegF32:$d), (ins RegI64:$a), "cvt.rn.f32.s64\t$d, $a", []>;
|
||||
: InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegI64:$a),
|
||||
"cvt$r.f32.s64\t$d, $a", []>;
|
||||
def CVTf32f64
|
||||
: InstPTX<(outs RegF32:$d), (ins RegF64:$a), "cvt.rn.f32.f64\t$d, $a", []>;
|
||||
: InstPTX<(outs RegF32:$d), (ins RndMode:$r, RegF64:$a),
|
||||
"cvt$r.f32.f64\t$d, $a", []>;
|
||||
|
||||
// To f64
|
||||
def CVTf64u16
|
||||
: InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.u16\t$d, $a", []>;
|
||||
: InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegI16:$a),
|
||||
"cvt$r.f64.u16\t$d, $a", []>;
|
||||
def CVTf64s16
|
||||
: InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.s16\t$d, $a", []>;
|
||||
: InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegI16:$a),
|
||||
"cvt$r.f64.s16\t$d, $a", []>;
|
||||
def CVTf64u32
|
||||
: InstPTX<(outs RegF64:$d), (ins RegI32:$a), "cvt.rn.f64.u32\t$d, $a", []>;
|
||||
: InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegI32:$a),
|
||||
"cvt$r.f64.u32\t$d, $a", []>;
|
||||
def CVTf64s32
|
||||
: InstPTX<(outs RegF64:$d), (ins RegI32:$a), "cvt.rn.f64.s32\t$d, $a", []>;
|
||||
: InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegI32:$a),
|
||||
"cvt$r.f64.s32\t$d, $a", []>;
|
||||
def CVTf64u64
|
||||
: InstPTX<(outs RegF64:$d), (ins RegI64:$a), "cvt.rn.f64.u64\t$d, $a", []>;
|
||||
: InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegI64:$a),
|
||||
"cvt$r.f64.u64\t$d, $a", []>;
|
||||
def CVTf64s64
|
||||
: InstPTX<(outs RegF64:$d), (ins RegI64:$a), "cvt.rn.f64.s64\t$d, $a", []>;
|
||||
: InstPTX<(outs RegF64:$d), (ins RndMode:$r, RegI64:$a),
|
||||
"cvt$r.f64.s64\t$d, $a", []>;
|
||||
def CVTf64f32
|
||||
: InstPTX<(outs RegF64:$d), (ins RegF32:$a), "cvt.f64.f32\t$d, $a", []>;
|
||||
|
||||
@ -889,10 +915,10 @@ def : Pat<(i16 (sext RegPred:$a)), (SELPi16ii RegPred:$a, 0xFFFF, 0)>;
|
||||
def : Pat<(i16 (zext RegPred:$a)), (SELPi16ii RegPred:$a, 1, 0)>;
|
||||
def : Pat<(i16 (trunc RegI32:$a)), (CVTu16u32 RegI32:$a)>;
|
||||
def : Pat<(i16 (trunc RegI64:$a)), (CVTu16u64 RegI64:$a)>;
|
||||
def : Pat<(i16 (fp_to_uint RegF32:$a)), (CVTu16f32 RegF32:$a)>;
|
||||
def : Pat<(i16 (fp_to_sint RegF32:$a)), (CVTs16f32 RegF32:$a)>;
|
||||
def : Pat<(i16 (fp_to_uint RegF64:$a)), (CVTu16f64 RegF64:$a)>;
|
||||
def : Pat<(i16 (fp_to_sint RegF64:$a)), (CVTs16f64 RegF64:$a)>;
|
||||
def : Pat<(i16 (fp_to_uint RegF32:$a)), (CVTu16f32 RndDefault, RegF32:$a)>;
|
||||
def : Pat<(i16 (fp_to_sint RegF32:$a)), (CVTs16f32 RndDefault, RegF32:$a)>;
|
||||
def : Pat<(i16 (fp_to_uint RegF64:$a)), (CVTu16f64 RndDefault, RegF64:$a)>;
|
||||
def : Pat<(i16 (fp_to_sint RegF64:$a)), (CVTs16f64 RndDefault, RegF64:$a)>;
|
||||
|
||||
// Conversion to u32
|
||||
def : Pat<(i32 (anyext RegPred:$a)), (SELPi32ii RegPred:$a, 1, 0)>;
|
||||
@ -902,10 +928,10 @@ def : Pat<(i32 (anyext RegI16:$a)), (CVTu32u16 RegI16:$a)>;
|
||||
def : Pat<(i32 (sext RegI16:$a)), (CVTs32s16 RegI16:$a)>;
|
||||
def : Pat<(i32 (zext RegI16:$a)), (CVTu32u16 RegI16:$a)>;
|
||||
def : Pat<(i32 (trunc RegI64:$a)), (CVTu32u64 RegI64:$a)>;
|
||||
def : Pat<(i32 (fp_to_uint RegF32:$a)), (CVTu32f32 RegF32:$a)>;
|
||||
def : Pat<(i32 (fp_to_sint RegF32:$a)), (CVTs32f32 RegF32:$a)>;
|
||||
def : Pat<(i32 (fp_to_uint RegF64:$a)), (CVTu32f64 RegF64:$a)>;
|
||||
def : Pat<(i32 (fp_to_sint RegF64:$a)), (CVTs32f64 RegF64:$a)>;
|
||||
def : Pat<(i32 (fp_to_uint RegF32:$a)), (CVTu32f32 RndDefault, RegF32:$a)>;
|
||||
def : Pat<(i32 (fp_to_sint RegF32:$a)), (CVTs32f32 RndDefault, RegF32:$a)>;
|
||||
def : Pat<(i32 (fp_to_uint RegF64:$a)), (CVTu32f64 RndDefault, RegF64:$a)>;
|
||||
def : Pat<(i32 (fp_to_sint RegF64:$a)), (CVTs32f64 RndDefault, RegF64:$a)>;
|
||||
def : Pat<(i32 (bitconvert RegF32:$a)), (MOVi32f32 RegF32:$a)>;
|
||||
|
||||
// Conversion to u64
|
||||
@ -919,33 +945,33 @@ def : Pat<(i64 (zext RegI16:$a)), (CVTu64u16 RegI16:$a)>;
|
||||
def : Pat<(i64 (anyext RegI32:$a)), (CVTu64u32 RegI32:$a)>;
|
||||
def : Pat<(i64 (sext RegI32:$a)), (CVTs64s32 RegI32:$a)>;
|
||||
def : Pat<(i64 (zext RegI32:$a)), (CVTu64u32 RegI32:$a)>;
|
||||
def : Pat<(i64 (fp_to_uint RegF32:$a)), (CVTu64f32 RegF32:$a)>;
|
||||
def : Pat<(i64 (fp_to_sint RegF32:$a)), (CVTs64f32 RegF32:$a)>;
|
||||
def : Pat<(i64 (fp_to_uint RegF64:$a)), (CVTu64f64 RegF64:$a)>;
|
||||
def : Pat<(i64 (fp_to_sint RegF64:$a)), (CVTs64f64 RegF64:$a)>;
|
||||
def : Pat<(i64 (fp_to_uint RegF32:$a)), (CVTu64f32 RndDefault, RegF32:$a)>;
|
||||
def : Pat<(i64 (fp_to_sint RegF32:$a)), (CVTs64f32 RndDefault, RegF32:$a)>;
|
||||
def : Pat<(i64 (fp_to_uint RegF64:$a)), (CVTu64f64 RndDefault, RegF64:$a)>;
|
||||
def : Pat<(i64 (fp_to_sint RegF64:$a)), (CVTs64f64 RndDefault, RegF64:$a)>;
|
||||
def : Pat<(i64 (bitconvert RegF64:$a)), (MOVi64f64 RegF64:$a)>;
|
||||
|
||||
// Conversion to f32
|
||||
def : Pat<(f32 (uint_to_fp RegPred:$a)), (SELPf32rr RegPred:$a,
|
||||
(MOVf32i32 0x3F800000), (MOVf32i32 0))>;
|
||||
def : Pat<(f32 (uint_to_fp RegI16:$a)), (CVTf32u16 RegI16:$a)>;
|
||||
def : Pat<(f32 (sint_to_fp RegI16:$a)), (CVTf32s16 RegI16:$a)>;
|
||||
def : Pat<(f32 (uint_to_fp RegI32:$a)), (CVTf32u32 RegI32:$a)>;
|
||||
def : Pat<(f32 (sint_to_fp RegI32:$a)), (CVTf32s32 RegI32:$a)>;
|
||||
def : Pat<(f32 (uint_to_fp RegI64:$a)), (CVTf32u64 RegI64:$a)>;
|
||||
def : Pat<(f32 (sint_to_fp RegI64:$a)), (CVTf32s64 RegI64:$a)>;
|
||||
def : Pat<(f32 (fround RegF64:$a)), (CVTf32f64 RegF64:$a)>;
|
||||
def : Pat<(f32 (uint_to_fp RegI16:$a)), (CVTf32u16 RndDefault, RegI16:$a)>;
|
||||
def : Pat<(f32 (sint_to_fp RegI16:$a)), (CVTf32s16 RndDefault, RegI16:$a)>;
|
||||
def : Pat<(f32 (uint_to_fp RegI32:$a)), (CVTf32u32 RndDefault, RegI32:$a)>;
|
||||
def : Pat<(f32 (sint_to_fp RegI32:$a)), (CVTf32s32 RndDefault, RegI32:$a)>;
|
||||
def : Pat<(f32 (uint_to_fp RegI64:$a)), (CVTf32u64 RndDefault, RegI64:$a)>;
|
||||
def : Pat<(f32 (sint_to_fp RegI64:$a)), (CVTf32s64 RndDefault, RegI64:$a)>;
|
||||
def : Pat<(f32 (fround RegF64:$a)), (CVTf32f64 RndDefault, RegF64:$a)>;
|
||||
def : Pat<(f32 (bitconvert RegI32:$a)), (MOVf32i32 RegI32:$a)>;
|
||||
|
||||
// Conversion to f64
|
||||
def : Pat<(f64 (uint_to_fp RegPred:$a)), (SELPf64rr RegPred:$a,
|
||||
(MOVf64i64 0x3F80000000000000), (MOVf64i64 0))>;
|
||||
def : Pat<(f64 (uint_to_fp RegI16:$a)), (CVTf64u16 RegI16:$a)>;
|
||||
def : Pat<(f64 (sint_to_fp RegI16:$a)), (CVTf64s16 RegI16:$a)>;
|
||||
def : Pat<(f64 (uint_to_fp RegI32:$a)), (CVTf64u32 RegI32:$a)>;
|
||||
def : Pat<(f64 (sint_to_fp RegI32:$a)), (CVTf64s32 RegI32:$a)>;
|
||||
def : Pat<(f64 (uint_to_fp RegI64:$a)), (CVTf64u64 RegI64:$a)>;
|
||||
def : Pat<(f64 (sint_to_fp RegI64:$a)), (CVTf64s64 RegI64:$a)>;
|
||||
def : Pat<(f64 (uint_to_fp RegI16:$a)), (CVTf64u16 RndDefault, RegI16:$a)>;
|
||||
def : Pat<(f64 (sint_to_fp RegI16:$a)), (CVTf64s16 RndDefault, RegI16:$a)>;
|
||||
def : Pat<(f64 (uint_to_fp RegI32:$a)), (CVTf64u32 RndDefault, RegI32:$a)>;
|
||||
def : Pat<(f64 (sint_to_fp RegI32:$a)), (CVTf64s32 RndDefault, RegI32:$a)>;
|
||||
def : Pat<(f64 (uint_to_fp RegI64:$a)), (CVTf64u64 RndDefault, RegI64:$a)>;
|
||||
def : Pat<(f64 (sint_to_fp RegI64:$a)), (CVTf64s64 RndDefault, RegI64:$a)>;
|
||||
def : Pat<(f64 (fextend RegF32:$a)), (CVTf64f32 RegF32:$a)>;
|
||||
def : Pat<(f64 (bitconvert RegI64:$a)), (MOVf64i64 RegI64:$a)>;
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user