mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-06-30 23:30:28 +00:00
Adjust to changes in Makefile.rules
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17167 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reid Spencer
parent
4d71b6611e
commit
8c2c3152d6
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@ -8,45 +8,13 @@
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##===----------------------------------------------------------------------===##
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LEVEL = ../../..
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LIBRARYNAME = powerpc
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include $(LEVEL)/Makefile.common
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TARGET = PowerPC
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# Make sure that tblgen is run, first thing.
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$(SourceDepend): PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \
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PowerPCGenAsmWriter.inc PPC32GenCodeEmitter.inc \
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BUILT_SOURCES = PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \
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PowerPCGenAsmWriter.inc PPC32GenCodeEmitter.inc \
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PPC32GenRegisterInfo.h.inc PPC32GenRegisterInfo.inc PPC32GenInstrInfo.inc \
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PPC64GenRegisterInfo.h.inc PPC64GenRegisterInfo.inc PPC64GenInstrInfo.inc
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TDFILES = $(wildcard $(SourceDir)/*.td) $(SourceDir)/../Target.td
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%GenRegisterNames.inc:: PPC32.td $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET) register names with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
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%GenRegisterInfo.h.inc:: %.td $(TDFILES) $(TBLGEN)
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@echo "Building `basename $<` register information header with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
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%GenRegisterInfo.inc:: %.td $(TDFILES) $(TBLGEN)
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@echo "Building `basename $<` register information implementation with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
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$(TARGET)GenInstrNames.inc:: PPC32.td $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET) instruction names with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
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%GenInstrInfo.inc:: %.td $(TDFILES) $(TBLGEN)
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@echo "Building `basename $<` instruction information with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
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%GenCodeEmitter.inc:: %.td $(TDFILES) $(TBLGEN)
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@echo "Building `basename $<` code emitter with tblgen"
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$(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@
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$(TARGET)GenAsmWriter.inc:: $(TARGET).td $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td assembly writer with tblgen"
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$(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-asm-writer -o $@
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clean::
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$(VERB) rm -f *.inc
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include $(LEVEL)/Makefile.common
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@ -2144,7 +2144,7 @@ bool PPC32ISel::emitBitfieldInsert(BinaryOperator *AndI, unsigned ShlAmount,
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if (CI_1 && OrI && OrI->getOpcode() == Instruction::Or) {
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Value *Op0 = OrI->getOperand(0);
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Value *Op1 = OrI->getOperand(1);
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BinaryOperator *AndI_2;
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BinaryOperator *AndI_2 = 0;
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// Whichever operand our initial And instruction is to the Or instruction,
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// Look at the other operand to determine if it is also an And instruction
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if (AndI == Op0) {
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@ -9,37 +9,11 @@
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LEVEL = ../../..
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LIBRARYNAME = skeleton
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include $(LEVEL)/Makefile.common
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TARGET = Skeleton
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TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \
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$(SourceDir)/../Target.td
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# Make sure that tblgen is run, first thing.
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$(SourceDepend): $(TARGET)GenRegisterInfo.h.inc $(TARGET)GenRegisterNames.inc \
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$(TARGET)GenRegisterInfo.inc $(TARGET)GenInstrNames.inc \
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$(TARGET)GenInstrInfo.inc
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BUILT_SOURCES = $(TARGET)GenRegisterInfo.h.inc $(TARGET)GenRegisterNames.inc \
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$(TARGET)GenRegisterInfo.inc $(TARGET)GenInstrNames.inc \
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$(TARGET)GenInstrInfo.inc
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$(TARGET)GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td register names with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
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$(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td register information header with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
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$(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td register information implementation with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
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$(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td instruction names with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
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$(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td instruction information with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
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clean::
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$(VERB) rm -f *.inc
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include $(LEVEL)/Makefile.common
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@ -10,48 +10,27 @@ LEVEL = ../../..
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LIBRARYNAME = sparcv9
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PARALLEL_DIRS = InstrSched LiveVar ModuloScheduling RegAlloc
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ExtraSource = SparcV9.burm.cpp
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BUILT_SOURCES = \
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SparcV9CodeEmitter.inc \
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SparcV9.burm.cpp
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include $(LEVEL)/Makefile.common
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ifdef ENABLE_OPTIMIZED
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DEBUG_FLAG =
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else
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DEBUG_FLAG = -D_DEBUG
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endif
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SparcV9.burg.in1 : $(BUILD_SRC_DIR)/SparcV9.burg.in
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$(CXX) -E $(CPPFLAGS) -x c++ $< | $(SED) '/^#/d' | $(SED) 's/Ydefine/#define/' > $@
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SparcV9.burg.in1 : $(SourceDir)/SparcV9.burg.in
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$(CXX) -E -I$(LLVM_SRC_ROOT)/include $(DEBUG_FLAG) -x c++ $< | $(SED) '/^#/d' | $(SED) 's/Ydefine/#define/' > $@
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SparcV9.burm : SparcV9.burg.in1 $(LLVM_SRC_ROOT)/include/llvm/Instruction.def
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$(CXX) -E -I$(LLVM_SRC_ROOT)/include $(DEBUG_FLAG) -x c++ $< | $(SED) '/^#/d' | $(SED) 's/^Xinclude/#include/' | $(SED) 's/^Xdefine/#define/' > $@
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SparcV9.burm : SparcV9.burg.in1
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$(CXX) -E $(CPPFLAGS) -x c++ $< | $(SED) '/^#/d' | $(SED) 's/^Xinclude/#include/' | $(SED) 's/^Xdefine/#define/' > $@
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SparcV9.burm.cpp: SparcV9.burm
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@echo "Burging `basename $<`"
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$(RunBurg) $< -o $@
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$(BURG) -I $< -o $@
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$(BUILD_OBJ_DIR)/Debug/SparcV9.burm.lo: SparcV9.burm.cpp
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$(CompileG) $< -o $@
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TABLEGEN_FILES := $(notdir $(wildcard $(BUILD_SRC_DIR)/*.td))
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$(BUILD_OBJ_DIR)/Release/SparcV9.burm.lo: SparcV9.burm.cpp
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$(CompileO) $< -o $@
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$(BUILD_OBJ_DIR)/Profile/SparcV9.burm.lo: SparcV9.burm.cpp
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$(CompileP) $< -o $@
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$(BUILD_OBJ_DIR)/Depend/SparcV9.burm.d: $(BUILD_OBJ_DIR)/Depend/.dir
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touch $@
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TABLEGEN_FILES := $(notdir $(wildcard $(SourceDir)/*.td))
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# Make sure that tblgen is run, first thing.
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$(SourceDepend): SparcV9CodeEmitter.inc
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SparcV9CodeEmitter.cpp:: SparcV9CodeEmitter.inc
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SparcV9CodeEmitter.inc:: $(SourceDir)/SparcV9.td $(TABLEGEN_FILES) $(TBLGEN)
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@echo "Tblgen'ing `basename $<`"
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$(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@
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SparcV9CodeEmitter.inc: $(BUILD_SRC_DIR)/SparcV9.td $(TABLEGEN_FILES) $(TBLGEN)
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@echo "Running tblgen on SparcV9.td"
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$(TableGen) -gen-emitter -o $@ $<
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clean::
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$(VERB) $(RM) -f SparcV9CodeEmitter.inc SparcV9.burg.in1 SparcV9.burm SparcV9.burm.cpp
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@ -8,50 +8,12 @@
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##===----------------------------------------------------------------------===##
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LEVEL = ../../..
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LIBRARYNAME = x86
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TARGET = X86
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
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X86GenRegisterInfo.inc X86GenInstrNames.inc \
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X86GenInstrInfo.inc X86GenATTAsmWriter.inc \
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X86GenIntelAsmWriter.inc
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include $(LEVEL)/Makefile.common
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TARGET = X86
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# Make sure that tblgen is run, first thing.
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$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
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X86GenRegisterInfo.inc X86GenInstrNames.inc \
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X86GenInstrInfo.inc X86GenATTAsmWriter.inc \
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X86GenIntelAsmWriter.inc
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TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \
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$(SourceDir)/../Target.td
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$(TARGET)GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td register names with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
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$(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td register information header with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
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$(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td register info implementation with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
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$(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td instruction names with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
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$(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td instruction information with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
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$(TARGET)GenATTAsmWriter.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td AT&T assembly writer with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -o $@
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$(TARGET)GenIntelAsmWriter.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td Intel assembly writer with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -asmwriternum=1 -o $@
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#$(TARGET)GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
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# @echo "Building $(TARGET).td instruction selector with tblgen"
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# $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
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clean::
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$(VERB) rm -f *.inc
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@ -10,7 +10,7 @@ LEVEL=..
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include $(LEVEL)/Makefile.config
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DIRS:= $(filter-out llvm-test,$(patsubst $(SourceDir)/%/Makefile,%,$(wildcard $(SourceDir)/*/Makefile)))
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DIRS:= $(filter-out llvm-test,$(patsubst $(BUILD_SRC_DIR)/%/Makefile,%,$(wildcard $(BUILD_SRC_DIR)/*/Makefile)))
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# Sparc cannot link shared libraries (libtool problem?) which Stacker uses
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ifeq ($(ARCH), Sparc)
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@ -18,3 +18,5 @@ include $(LEVEL)/Makefile.common
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ifdef PARSE_DEBUG
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INCLUDES += -DPARSE_DEBUG
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endif
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$(OBJDIR)/Lexer.o : StackerParser.h
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@ -14,7 +14,7 @@ TOOLNAME=sample
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# List libraries that we'll need
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# We use LIBS because sample is a dynamic library.
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#
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LIBS+=-lsample
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USEDLIBS = sample
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#
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# Include Makefile.common so we know what to do.
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@ -9,11 +9,9 @@
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LEVEL = ../../..
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BYTECODE_LIBRARY=1
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#SHARED_LIBRARY=1
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#DONT_BUILD_RELINKED=1
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LIBRARYNAME=gcsemispace
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EXPORTED_SYMBOL_FILE = $(SourceDir)/../gc_exported_symbols.lst
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EXPORTED_SYMBOL_FILE = $(BUILD_SRC_DIR)/../gc_exported_symbols.lst
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include $(LEVEL)/Makefile.common
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@ -21,18 +21,17 @@ DONT_BUILD_RELINKED=1
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MainSrc := crtend.c listend.ll
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GenericEHSrc := Exception.cpp
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SJLJEHSrc := SJLJ-Exception.cpp
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CXXEHSrc := C++-Exception.cpp
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Source := $(MainSrc) $(GenericEHSrc) $(SJLJEHSrc) $(CXXEHSrc)
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include $(LEVEL)/Makefile.common
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# CRTEND_A - The result of making 'all' - the final archive file.
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CRTEND_A = $(DESTLIBBYTECODE)/libcrtend.a
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CRTEND_A = $(LIBDIR)/libcrtend.a
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all:: $(CRTEND_A)
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# Installation simply requires copying the archive to it's new home.
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$(DESTDIR)$(bytecode_libdir)/libcrtend.a: $(CRTEND_A) $(DESTDIR)$(bytecode_libdir)
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cp $< $@
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$(DESTDIR)$(bytecode_libdir)/libcrtend.a: $(CRTEND_A)
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$(INSTALL) $(CRTEND_A) $(DESTDIR)$(bytecode_libdir)
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install:: $(DESTDIR)$(bytecode_libdir)/libcrtend.a
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install-bytecode:: $(DESTDIR)$(bytecode_libdir)/libcrtend.a
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@ -40,33 +39,31 @@ install-bytecode:: $(DESTDIR)$(bytecode_libdir)/libcrtend.a
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# The four components described in the README
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Components := main genericeh sjljeh
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ComponentLibs := $(Components:%=$(BUILD_OBJ_DIR)/BytecodeObj/comp_%.bc)
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ComponentLibs := $(Components:%=$(OBJDIR)/comp_%.bc)
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# We build libcrtend.a from the four components described in the README.
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$(CRTEND_A) : $(ComponentLibs) $(DESTLIBBYTECODE)/.dir
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$(CRTEND_A) : $(ComponentLibs) $(LIBDIR)/.dir
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@echo Building final libcrtend.a file from components
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$(VERB) $(AR) $@ $(ComponentLibs)
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$(VERB) $(Archive) $@ $(ComponentLibs)
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MainObj := $(BUILD_OBJ_DIR)/BytecodeObj/crtend.bc \
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$(BUILD_OBJ_DIR)/BytecodeObj/listend.bc
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GenericEHObj := $(BUILD_OBJ_DIR)/BytecodeObj/Exception.bc
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SJLJEHObj := $(BUILD_OBJ_DIR)/BytecodeObj/SJLJ-Exception.bc
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CXXEHObj := $(BUILD_OBJ_DIR)/BytecodeObj/C++-Exception.bc
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MainObj := $(OBJDIR)/crtend.bc $(OBJDIR)/listend.bc
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GenericEHObj := $(OBJDIR)/Exception.bc
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SJLJEHObj := $(OBJDIR)/SJLJ-Exception.bc
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# __main and ctor/dtor support component
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$(BUILD_OBJ_DIR)/BytecodeObj/comp_main.bc: $(MainObj)
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$(OBJDIR)/comp_main.bc: $(MainObj)
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@echo Linking $(notdir $@) component...
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$(VERB) $(LGCCLDPROG) -link-as-library -internalize-public-api-file=$(BUILD_SRC_DIR)/comp_main.lst $(MainObj) -o $@
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$(VERB) $(GCCLD) -link-as-library -internalize-public-api-file=$(BUILD_SRC_DIR)/comp_main.lst $(MainObj) -o $@
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# Generic exception handling support runtime.
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$(BUILD_OBJ_DIR)/BytecodeObj/comp_genericeh.bc: $(GenericEHObj)
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$(OBJDIR)/comp_genericeh.bc: $(GenericEHObj)
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@echo Linking $(notdir $@) component...
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$(VERB) $(LGCCLDPROG) -link-as-library -internalize-public-api-file=$(BUILD_SRC_DIR)/comp_genericeh.lst $(GenericEHObj) -o $@
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$(VERB) $(GCCLD) -link-as-library -internalize-public-api-file=$(BUILD_SRC_DIR)/comp_genericeh.lst $(GenericEHObj) -o $@
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# setjmp/longjmp exception handling support runtime.
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$(BUILD_OBJ_DIR)/BytecodeObj/comp_sjljeh.bc: $(SJLJEHObj)
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$(OBJDIR)/comp_sjljeh.bc: $(SJLJEHObj)
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@echo Linking $(notdir $@) component...
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$(VERB) $(LGCCLDPROG) -link-as-library -internalize-public-api-file=$(BUILD_SRC_DIR)/comp_sjljeh.lst $(SJLJEHObj) -o $@
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$(VERB) $(GCCLD) -link-as-library -internalize-public-api-file=$(BUILD_SRC_DIR)/comp_sjljeh.lst $(SJLJEHObj) -o $@
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@ -6,6 +6,7 @@
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# the University of Illinois Open Source License. See LICENSE.TXT for details.
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#
|
||||
##===----------------------------------------------------------------------===##
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|
||||
LEVEL = ../../..
|
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BYTECODE_LIBRARY=1
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DONT_BUILD_RELINKED=1
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|
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@ -8,7 +8,7 @@
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##===----------------------------------------------------------------------===##
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LEVEL = ../..
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TOOLNAME = burg
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ExtraSource = gram.tab.c
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BUILT_SOURCES = gram.tab.c
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include $(LEVEL)/Makefile.common
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