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Fix a bug in merged condition handling (CodeGen/Generic/2006-10-27-CondFolding.ll).
Add many fewer CFG edges and PHI node entries. If there is a switch which has the same block as multiple destinations, only add that block once as a successor/phi node (in the jumptable case) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31242 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -282,24 +282,24 @@ FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
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// Create Machine PHI nodes for LLVM PHI nodes, lowering them as
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// appropriate.
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PHINode *PN;
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for (BasicBlock::iterator I = BB->begin();
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(PN = dyn_cast<PHINode>(I)); ++I)
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if (!PN->use_empty()) {
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MVT::ValueType VT = TLI.getValueType(PN->getType());
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unsigned NumElements;
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if (VT != MVT::Vector)
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NumElements = TLI.getNumElements(VT);
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else {
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MVT::ValueType VT1,VT2;
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NumElements =
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TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
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VT1, VT2);
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}
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unsigned PHIReg = ValueMap[PN];
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assert(PHIReg &&"PHI node does not have an assigned virtual register!");
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for (unsigned i = 0; i != NumElements; ++i)
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BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
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for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
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if (PN->use_empty()) continue;
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MVT::ValueType VT = TLI.getValueType(PN->getType());
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unsigned NumElements;
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if (VT != MVT::Vector)
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NumElements = TLI.getNumElements(VT);
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else {
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MVT::ValueType VT1,VT2;
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NumElements =
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TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
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VT1, VT2);
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}
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unsigned PHIReg = ValueMap[PN];
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assert(PHIReg && "PHI node does not have an assigned virtual register!");
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for (unsigned i = 0; i != NumElements; ++i)
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BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
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}
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}
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}
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@ -497,6 +497,7 @@ public:
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void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
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unsigned Opc);
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bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
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void ExportFromCurrentBlock(Value *V);
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// Terminator instructions.
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@ -798,15 +799,39 @@ void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
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PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
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}
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bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
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const BasicBlock *FromBB) {
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// The operands of the setcc have to be in this block. We don't know
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// how to export them from some other block.
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if (Instruction *VI = dyn_cast<Instruction>(V)) {
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// Can export from current BB.
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if (VI->getParent() == FromBB)
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return true;
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// Is already exported, noop.
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return FuncInfo.isExportedInst(V);
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}
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// If this is an argument, we can export it if the BB is the entry block or
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// if it is already exported.
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if (isa<Argument>(V)) {
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if (FromBB == &FromBB->getParent()->getEntryBlock())
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return true;
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// Otherwise, can only export this if it is already exported.
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return FuncInfo.isExportedInst(V);
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}
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// Otherwise, constants can always be exported.
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return true;
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}
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/// FindMergedConditions - If Cond is an expression like
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void SelectionDAGLowering::FindMergedConditions(Value *Cond,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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MachineBasicBlock *CurBB,
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unsigned Opc) {
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// FIXME: HANDLE AND.
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// FIXME: HANDLE NOT
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// If this node is not part of the or/and tree, emit it as a branch.
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BinaryOperator *BOp = dyn_cast<BinaryOperator>(Cond);
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@ -819,12 +844,8 @@ void SelectionDAGLowering::FindMergedConditions(Value *Cond,
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if (BOp && isa<SetCondInst>(BOp) &&
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// The operands of the setcc have to be in this block. We don't know
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// how to export them from some other block.
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(!isa<Instruction>(BOp->getOperand(0)) ||
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cast<Instruction>(BOp->getOperand(0))->getParent() == BB ||
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FuncInfo.isExportedInst(BOp->getOperand(0))) &&
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(!isa<Instruction>(BOp->getOperand(1)) ||
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cast<Instruction>(BOp->getOperand(1))->getParent() == BB ||
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FuncInfo.isExportedInst(BOp->getOperand(1)))) {
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isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
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isExportableFromCurrentBlock(BOp->getOperand(1), BB)) {
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ExportFromCurrentBlock(BOp->getOperand(0));
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ExportFromCurrentBlock(BOp->getOperand(1));
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@ -1222,10 +1243,18 @@ void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
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DestBBs.push_back(Default);
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}
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// Update successor info
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// Update successor info. Add one edge to each unique successor.
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// Vector bool would be better, but vector<bool> is really slow.
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std::vector<unsigned char> SuccsHandled;
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SuccsHandled.resize(CurMBB->getParent()->getNumBlockIDs());
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for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
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E = DestBBs.end(); I != E; ++I)
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JumpTableBB->addSuccessor(*I);
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E = DestBBs.end(); I != E; ++I) {
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if (!SuccsHandled[(*I)->getNumber()]) {
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SuccsHandled[(*I)->getNumber()] = true;
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JumpTableBB->addSuccessor(*I);
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}
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}
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// Create a jump table index for this jump table, or return an existing
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// one.
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@ -3710,63 +3739,77 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
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// BB. As such, the start of the BB might correspond to a different MBB than
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// the end.
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//
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TerminatorInst *TI = LLVMBB->getTerminator();
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// Emit constants only once even if used by multiple PHI nodes.
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std::map<Constant*, unsigned> ConstantsOut;
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// Vector bool would be better, but vector<bool> is really slow.
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std::vector<unsigned char> SuccsHandled;
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if (TI->getNumSuccessors())
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SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
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// Check successor nodes PHI nodes that expect a constant to be available from
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// this block.
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TerminatorInst *TI = LLVMBB->getTerminator();
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for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
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BasicBlock *SuccBB = TI->getSuccessor(succ);
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if (!isa<PHINode>(SuccBB->begin())) continue;
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MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
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MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
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// If this terminator has multiple identical successors (common for
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// switches), only handle each succ once.
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unsigned SuccMBBNo = SuccMBB->getNumber();
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if (SuccsHandled[SuccMBBNo]) continue;
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SuccsHandled[SuccMBBNo] = true;
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MachineBasicBlock::iterator MBBI = SuccMBB->begin();
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PHINode *PN;
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// At this point we know that there is a 1-1 correspondence between LLVM PHI
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// nodes and Machine PHI nodes, but the incoming operands have not been
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// emitted yet.
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for (BasicBlock::iterator I = SuccBB->begin();
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(PN = dyn_cast<PHINode>(I)); ++I)
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if (!PN->use_empty()) {
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unsigned Reg;
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Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
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if (Constant *C = dyn_cast<Constant>(PHIOp)) {
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unsigned &RegOut = ConstantsOut[C];
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if (RegOut == 0) {
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RegOut = FuncInfo.CreateRegForValue(C);
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UnorderedChains.push_back(
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SDL.CopyValueToVirtualRegister(C, RegOut));
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}
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Reg = RegOut;
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} else {
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Reg = FuncInfo.ValueMap[PHIOp];
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if (Reg == 0) {
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assert(isa<AllocaInst>(PHIOp) &&
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FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
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"Didn't codegen value into a register!??");
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Reg = FuncInfo.CreateRegForValue(PHIOp);
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UnorderedChains.push_back(
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SDL.CopyValueToVirtualRegister(PHIOp, Reg));
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}
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(PN = dyn_cast<PHINode>(I)); ++I) {
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// Ignore dead phi's.
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if (PN->use_empty()) continue;
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unsigned Reg;
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Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
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if (Constant *C = dyn_cast<Constant>(PHIOp)) {
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unsigned &RegOut = ConstantsOut[C];
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if (RegOut == 0) {
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RegOut = FuncInfo.CreateRegForValue(C);
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UnorderedChains.push_back(
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SDL.CopyValueToVirtualRegister(C, RegOut));
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}
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// Remember that this register needs to added to the machine PHI node as
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// the input for this MBB.
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MVT::ValueType VT = TLI.getValueType(PN->getType());
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unsigned NumElements;
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if (VT != MVT::Vector)
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NumElements = TLI.getNumElements(VT);
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else {
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MVT::ValueType VT1,VT2;
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NumElements =
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TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
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VT1, VT2);
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Reg = RegOut;
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} else {
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Reg = FuncInfo.ValueMap[PHIOp];
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if (Reg == 0) {
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assert(isa<AllocaInst>(PHIOp) &&
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FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
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"Didn't codegen value into a register!??");
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Reg = FuncInfo.CreateRegForValue(PHIOp);
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UnorderedChains.push_back(
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SDL.CopyValueToVirtualRegister(PHIOp, Reg));
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}
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for (unsigned i = 0, e = NumElements; i != e; ++i)
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PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
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}
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// Remember that this register needs to added to the machine PHI node as
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// the input for this MBB.
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MVT::ValueType VT = TLI.getValueType(PN->getType());
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unsigned NumElements;
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if (VT != MVT::Vector)
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NumElements = TLI.getNumElements(VT);
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else {
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MVT::ValueType VT1,VT2;
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NumElements =
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TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
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VT1, VT2);
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}
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for (unsigned i = 0, e = NumElements; i != e; ++i)
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PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
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}
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}
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ConstantsOut.clear();
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