6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-01 15:11:24 +00:00
Code Issues Projects Releases Wiki Activity

Silence Release-Asserts warnings.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72011 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Dunbar 2009-05-18 16:43:04 +00:00
parent 10978bd591
commit 8c562e2d25
3 changed files with 11 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/Analysis/ScalarEvolution.cpp
View File

@ -3081,6 +3081,7 @@ SCEVHandle ScalarEvolution::getSCEVAtScope(const SCEV *V, const Loop *L) {
} }
assert(0 && "Unknown SCEV type!"); assert(0 && "Unknown SCEV type!");
return 0;
} }
/// getSCEVAtScope - This is a convenience function which does /// getSCEVAtScope - This is a convenience function which does

12
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -6000,9 +6000,9 @@ void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
// Get alias information for node. // Get alias information for node.
SDValue Ptr; SDValue Ptr;
int64_t Size; int64_t Size = 0;
const Value *SrcValue; const Value *SrcValue = 0;
int SrcValueOffset; int SrcValueOffset = 0;
bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
// Starting off. // Starting off.
@ -6028,9 +6028,9 @@ void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
case ISD::STORE: { case ISD::STORE: {
// Get alias information for Chain. // Get alias information for Chain.
SDValue OpPtr; SDValue OpPtr;
int64_t OpSize; int64_t OpSize = 0;
const Value *OpSrcValue; const Value *OpSrcValue = 0;
int OpSrcValueOffset; int OpSrcValueOffset = 0;
bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
OpSrcValue, OpSrcValueOffset); OpSrcValue, OpSrcValueOffset);

4
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
View File

@ -119,6 +119,7 @@ void ScheduleDAGSDNodes::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
DstRC, SrcRC); DstRC, SrcRC);
assert(Emitted && "Unable to issue a copy instruction!\n"); assert(Emitted && "Unable to issue a copy instruction!\n");
(void) Emitted;
} }
SDValue Op(Node, ResNo); SDValue Op(Node, ResNo);
@ -254,6 +255,7 @@ ScheduleDAGSDNodes::AddRegisterOperand(MachineInstr *MI, SDValue Op,
bool Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg, bool Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg,
DstRC, SrcRC); DstRC, SrcRC);
assert(Emitted && "Unable to issue a copy instruction!\n"); assert(Emitted && "Unable to issue a copy instruction!\n");
(void) Emitted;
VReg = NewVReg; VReg = NewVReg;
} }
} }
@ -445,6 +447,7 @@ ScheduleDAGSDNodes::EmitCopyToRegClassNode(SDNode *Node,
DstRC, SrcRC); DstRC, SrcRC);
assert(Emitted && assert(Emitted &&
"Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n"); "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n");
(void) Emitted;
SDValue Op(Node, 0); SDValue Op(Node, 0);
bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
@ -568,6 +571,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
bool Emitted = TII->copyRegToReg(*BB, InsertPos, DestReg, SrcReg, bool Emitted = TII->copyRegToReg(*BB, InsertPos, DestReg, SrcReg,
DstTRC, SrcTRC); DstTRC, SrcTRC);
assert(Emitted && "Unable to issue a copy instruction!\n"); assert(Emitted && "Unable to issue a copy instruction!\n");
(void) Emitted;
break; break;
} }
case ISD::CopyFromReg: { case ISD::CopyFromReg: {