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[PowerPC] Implement the vpopcnt instructions for POWER8
Patch by Kit Barton.
Add the vector population count instructions for byte, halfword, word,
and doubleword sizes. There are two major changes here:
PPCISelLowering.cpp: Make CTPOP legal for vector types.
PPCRegisterInfo.td: Added v2i64 to the VRRC register
definition. This is needed for the doubleword variations of the
integer ops that were added in P8.
Test Plan
Test the instruction vpcnt* encoding/decoding in ppc64-encoding-vmx.s
Test the generation of the vpopcnt instructions for various vector
data types. When adding the v2i64 type to the Vector Register set, I
also needed to add the appropriate bit conversion patterns between
v2i64 and the existing vector types. Testing for these conversions
were also added in the test case by passing a different vector type as
a parameter into the test functions. There is also a run step that
will ensure the vpopcnt instructions are generated when the vsx
feature is disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228046 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Schmidt
parent
04e540582b
commit
8c775a4e7b
@ -109,9 +109,12 @@ def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
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def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
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"Enable VSX instructions",
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[FeatureAltivec]>;
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def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
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"Enable POWER8 Altivec instructions",
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[FeatureAltivec]>;
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def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
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"Enable POWER8 vector instructions",
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[FeatureVSX, FeatureAltivec]>;
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[FeatureVSX, FeatureP8Altivec]>;
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def FeatureInvariantFunctionDescriptors :
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SubtargetFeature<"invariant-function-descriptors",
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@ -260,9 +263,9 @@ def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
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*/
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def ProcessorFeatures {
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list<SubtargetFeature> Power8FeatureList =
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[DirectivePwr8, FeatureAltivec, FeatureVSX, FeatureP8Vector,
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FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
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FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
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[DirectivePwr8, FeatureAltivec, FeatureP8Altivec, FeatureVSX,
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FeatureP8Vector, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt,
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FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
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FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
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FeatureFPRND, FeatureFPCVT, FeatureISEL,
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FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
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@ -401,6 +401,12 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::ADD , VT, Legal);
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setOperationAction(ISD::SUB , VT, Legal);
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// Vector popcnt instructions introduced in P8
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if (Subtarget.hasP8Altivec())
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setOperationAction(ISD::CTPOP, VT, Legal);
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else
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setOperationAction(ISD::CTPOP, VT, Expand);
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// We promote all shuffles to v16i8.
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
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AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
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@ -455,7 +461,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
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setOperationAction(ISD::FPOW, VT, Expand);
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setOperationAction(ISD::BSWAP, VT, Expand);
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setOperationAction(ISD::CTPOP, VT, Expand);
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setOperationAction(ISD::CTLZ, VT, Expand);
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setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
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setOperationAction(ISD::CTTZ, VT, Expand);
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@ -593,6 +598,9 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
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}
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if (Subtarget.hasP8Altivec())
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addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
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}
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if (Subtarget.has64BitSupport())
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@ -791,18 +791,27 @@ def : Pat<(store v4i32:$rS, xoaddr:$dst),
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def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
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def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
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def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
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def : Pat<(v16i8 (bitconvert (v2i64 VRRC:$src))), (v16i8 VRRC:$src)>;
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def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
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def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
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def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
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def : Pat<(v8i16 (bitconvert (v2i64 VRRC:$src))), (v8i16 VRRC:$src)>;
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def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
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def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
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def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
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def : Pat<(v4i32 (bitconvert (v2i64 VRRC:$src))), (v4i32 VRRC:$src)>;
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def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
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def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
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def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
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def : Pat<(v4f32 (bitconvert (v2i64 VRRC:$src))), (v4f32 VRRC:$src)>;
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def : Pat<(v2i64 (bitconvert (v16i8 VRRC:$src))), (v2i64 VRRC:$src)>;
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def : Pat<(v2i64 (bitconvert (v8i16 VRRC:$src))), (v2i64 VRRC:$src)>;
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def : Pat<(v2i64 (bitconvert (v4i32 VRRC:$src))), (v2i64 VRRC:$src)>;
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def : Pat<(v2i64 (bitconvert (v4f32 VRRC:$src))), (v2i64 VRRC:$src)>;
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// Shuffles.
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@ -929,3 +938,19 @@ def : Pat<(v4f32 (fnearbyint v4f32:$vA)),
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} // end HasAltivec
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def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">;
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let Predicates = [HasP8Altivec] in {
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// Population Count
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def VPOPCNTB : VXForm_2<1795, (outs vrrc:$vD), (ins vrrc:$vB),
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"vpopcntb $vD, $vB", IIC_VecGeneral,
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[(set v16i8:$vD, (ctpop v16i8:$vB))]>;
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def VPOPCNTH : VXForm_2<1859, (outs vrrc:$vD), (ins vrrc:$vB),
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"vpopcnth $vD, $vB", IIC_VecGeneral,
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[(set v8i16:$vD, (ctpop v8i16:$vB))]>;
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def VPOPCNTW : VXForm_2<1923, (outs vrrc:$vD), (ins vrrc:$vB),
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"vpopcntw $vD, $vB", IIC_VecGeneral,
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[(set v4i32:$vD, (ctpop v4i32:$vB))]>;
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def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB),
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"vpopcntd $vD, $vB", IIC_VecGeneral,
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[(set v2i64:$vD, (ctpop v2i64:$vB))]>;
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} // end HasP8Altivec
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@ -275,7 +275,7 @@ def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),
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(sequence "F%u", 31, 14))>;
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def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
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def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
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def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v2i64,v4f32], 128,
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(add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
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V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
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V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>;
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@ -65,6 +65,7 @@ void PPCSubtarget::initializeEnvironment() {
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HasQPX = false;
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HasVSX = false;
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HasP8Vector = false;
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HasP8Altivec = false;
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HasFCPSGN = false;
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HasFSQRT = false;
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HasFRE = false;
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@ -89,6 +89,7 @@ protected:
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bool HasQPX;
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bool HasVSX;
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bool HasP8Vector;
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bool HasP8Altivec;
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bool HasFCPSGN;
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bool HasFSQRT;
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bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
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@ -216,6 +217,7 @@ public:
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bool hasQPX() const { return HasQPX; }
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bool hasVSX() const { return HasVSX; }
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bool hasP8Vector() const { return HasP8Vector; }
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bool hasP8Altivec() const { return HasP8Altivec; }
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bool hasMFOCRF() const { return HasMFOCRF; }
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bool hasISEL() const { return HasISEL; }
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bool hasPOPCNTD() const { return HasPOPCNTD; }
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@ -501,6 +501,18 @@
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# CHECK: vrsqrtefp 2, 3
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0x10 0x40 0x19 0x4a
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# CHECK: vpopcntb 2, 3
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0x10 0x40 0x1f 0x03
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# CHECK: vpopcnth 2, 3
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0x10 0x40 0x1f 0x43
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# CHECK: vpopcntw 2, 3
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0x10 0x40 0x1f 0x83
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# CHECK: vpopcntd 2, 3
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0x10 0x40 0x1f 0xc3
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# CHECK: mtvscr 2
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0x10 0x00 0x16 0x44
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@ -543,6 +543,23 @@
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# CHECK-LE: vrsqrtefp 2, 3 # encoding: [0x4a,0x19,0x40,0x10]
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vrsqrtefp 2, 3
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# Vector population count instructions
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# CHECK-BE: vpopcntb 2, 3 # encoding: [0x10,0x40,0x1f,0x03]
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# CHECK-LE: vpopcntb 2, 3 # encoding: [0x03,0x1f,0x40,0x10]
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vpopcntb 2, 3
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# CHECK-BE: vpopcnth 2, 3 # encoding: [0x10,0x40,0x1f,0x43]
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# CHECK-LE: vpopcnth 2, 3 # encoding: [0x43,0x1f,0x40,0x10]
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vpopcnth 2, 3
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# CHECK-BE: vpopcntw 2, 3 # encoding: [0x10,0x40,0x1f,0x83]
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# CHECK-LE: vpopcntw 2, 3 # encoding: [0x83,0x1f,0x40,0x10]
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vpopcntw 2, 3
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# BCHECK-BE: vpopcntd 2, 3 # encoding: [0x10,0x40,0x1f,0xC3]
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# BCHECK-LE: vpopcntd 2, 3 # encoding: [0xC3,0x1f,0x40,0x10]
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# vpopcntd 2, 3
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# Vector status and control register instructions
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# CHECK-BE: mtvscr 2 # encoding: [0x10,0x00,0x16,0x44]
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