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Implement cond ? -1 : 0 with sbb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94490 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3220,6 +3220,14 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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NegOne, DAG.getConstant(0, VT),
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NegOne, DAG.getConstant(0, VT),
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cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
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cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
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if (SCC.getNode()) return SCC;
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if (SCC.getNode()) return SCC;
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if (!LegalOperations ||
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TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
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return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
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DAG.getSetCC(N->getDebugLoc(),
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TLI.getSetCCResultType(VT),
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N0.getOperand(0), N0.getOperand(1),
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cast<CondCodeSDNode>(N0.getOperand(2))->get()),
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NegOne, DAG.getConstant(0, VT));
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}
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}
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@ -5965,6 +5965,29 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
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Cond = NewCond;
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Cond = NewCond;
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}
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}
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// (select (x == 0), -1, 0) -> (sign_bit (x - 1))
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SDValue Op1 = Op.getOperand(1);
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SDValue Op2 = Op.getOperand(2);
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if (Cond.getOpcode() == X86ISD::SETCC &&
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cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
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SDValue Cmp = Cond.getOperand(1);
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if (Cmp.getOpcode() == X86ISD::CMP) {
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
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ConstantSDNode *RHSC =
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dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
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if (N1C && N1C->isAllOnesValue() &&
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N2C && N2C->isNullValue() &&
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RHSC && RHSC->isNullValue()) {
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SDValue CmpOp0 = Cmp.getOperand(0);
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Cmp = DAG.getNode(X86ISD::CMP, dl, Op.getValueType(),
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CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
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return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
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DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
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}
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}
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}
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// Look pass (and (setcc_carry (cmp ...)), 1).
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// Look pass (and (setcc_carry (cmp ...)), 1).
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if (Cond.getOpcode() == ISD::AND &&
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if (Cond.getOpcode() == ISD::AND &&
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Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
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Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
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@ -6017,10 +6040,10 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
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Cond = EmitTest(Cond, X86::COND_NE, DAG);
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Cond = EmitTest(Cond, X86::COND_NE, DAG);
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}
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}
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SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
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// X86ISD::CMOV means set the result (which is operand 1) to the RHS if
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// X86ISD::CMOV means set the result (which is operand 1) to the RHS if
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// condition is true.
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// condition is true.
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SDValue Ops[] = { Op.getOperand(2), Op.getOperand(1), CC, Cond };
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SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
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SDValue Ops[] = { Op2, Op1, CC, Cond };
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return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
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return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
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}
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}
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22
test/CodeGen/X86/sext-i1.ll
Normal file
22
test/CodeGen/X86/sext-i1.ll
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@ -0,0 +1,22 @@
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; RUN: llc < %s -march=x86 | FileCheck %s
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; rdar://7573216
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define i32 @t1(i32 %x) nounwind readnone ssp {
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entry:
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; CHECK: t1:
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; CHECK: cmpl $1
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; CHECK: sbbl
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%0 = icmp eq i32 %x, 0
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%iftmp.0.0 = select i1 %0, i32 -1, i32 0
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ret i32 %iftmp.0.0
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}
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define i32 @t2(i32 %x) nounwind readnone ssp {
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entry:
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; CHECK: t2:
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; CHECK: cmpl $1
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; CHECK: sbbl
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%0 = icmp eq i32 %x, 0
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%iftmp.0.0 = sext i1 %0 to i32
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ret i32 %iftmp.0.0
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}
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