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Predicate encoding should be withing {}s. And general cleanup.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120361 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2010-11-30 00:08:20 +00:00
parent 194271a76e
commit 8ca2fd6665
2 changed files with 4 additions and 8 deletions

8
lib/Target/ARM/ARMInstrInfo.td

@ -1177,19 +1177,17 @@ def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
// LEApcrel - Load a pc-relative address into a register without offending the
// assembler.
let neverHasSideEffects = 1 in {
let isReMaterializable = 1 in
let neverHasSideEffects = 1, isReMaterializable = 1 in
// FIXME: We want one cannonical LEApcrel instruction and to express one or
// both of these as pseudo-instructions that get expanded to it.
def LEApcrel : AXI1<0, (outs GPR:$Rd), (ins i32imm:$label, pred:$p),
MiscFrm, IIC_iALUi,
"adr$p\t$Rd, #$label", []>;
"adr${p}\t$Rd, #$label", []>;
} // neverHasSideEffects
def LEApcrelJT : AXI1<0b0100, (outs GPR:$Rd),
(ins i32imm:$label, nohash_imm:$id, pred:$p),
MiscFrm, IIC_iALUi,
"adr$p\t$Rd, #${label}_${id}", []> {
"adr${p}\t$Rd, #${label}_${id}", []> {
bits<4> p;
bits<4> Rd;
let Inst{31-28} = p;

4
lib/Target/ARM/ARMInstrThumb.td

@ -1240,13 +1240,11 @@ def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
// tLEApcrel - Load a pc-relative address into a register without offending the
// assembler.
let neverHasSideEffects = 1 in {
let isReMaterializable = 1 in
let neverHasSideEffects = 1, isReMaterializable = 1 in
def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
"adr${p}\t$dst, #$label", []>,
T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
} // neverHasSideEffects
def tLEApcrelJT : T1I<(outs tGPR:$dst),
(ins i32imm:$label, nohash_imm:$id, pred:$p),
IIC_iALUi, "adr${p}\t$dst, #${label}_${id}", []>,