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Add predicates methods to TargetOperandInfo, and switch all clients
over to using them, instead of diddling Flags directly. Change the various flags from const variables to enums. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45677 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -32,14 +32,14 @@ class SelectionDAG;
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template<class T> class SmallVectorImpl;
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//---------------------------------------------------------------------------
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//===----------------------------------------------------------------------===//
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// Data types used to define information about a single machine instruction
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//---------------------------------------------------------------------------
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//===----------------------------------------------------------------------===//
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typedef short MachineOpCode;
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typedef unsigned InstrSchedClass;
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//---------------------------------------------------------------------------
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//===----------------------------------------------------------------------===//
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// struct TargetInstrDescriptor:
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// Predefined information about each machine instruction.
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// Designed to initialized statically.
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@ -124,24 +124,25 @@ const unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 18;
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// both! If neither flag is set, then the instruction *always* has side effects.
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const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19;
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//===----------------------------------------------------------------------===//
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// Machine operand flags
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// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
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// requires a callback to look up its register class.
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const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
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/// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of the
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/// predicate operand that controls an M_PREDICATED instruction.
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const unsigned M_PREDICATE_OPERAND = 1 << 1;
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/// M_OPTIONAL_DEF_OPERAND - Set if this operand is a optional def.
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///
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const unsigned M_OPTIONAL_DEF_OPERAND = 1 << 2;
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//===----------------------------------------------------------------------===//
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namespace TOI {
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// Operand constraints: only "tied_to" for now.
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enum OperandConstraint {
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TIED_TO = 0 // Must be allocated the same register as.
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};
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/// OperandFlags - These are flags set on operands, but should be considered
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/// private, all access should go through the TargetOperandInfo accessors.
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/// See the accessors for a description of what these are.
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enum OperandFlags {
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LookupPtrRegClass = 1 << 0,
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Predicate = 1 << 1,
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OptionalDef = 1 << 2
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};
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}
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/// TargetOperandInfo - This holds information about one operand of a machine
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@ -157,6 +158,18 @@ public:
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/// bits are used to specify the value of constraints (4 bits each).
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unsigned int Constraints;
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/// Currently no other information.
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/// isLookupPtrRegClass - Set if this operand is a pointer value and it
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/// requires a callback to look up its register class.
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bool isLookupPtrRegClass() const { return Flags & TOI::LookupPtrRegClass; }
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/// isPredicate - Set if this is one of the operands that made up of
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/// the predicate operand that controls an M_PREDICATED instruction.
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bool isPredicate() const { return Flags & TOI::Predicate; }
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/// isOptionalDef - Set if this operand is a optional def.
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///
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bool isOptionalDef() const { return Flags & TOI::OptionalDef; }
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};
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@ -541,7 +541,7 @@ int MachineInstr::findFirstPredOperandIdx() const {
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const TargetInstrDescriptor *TID = getDesc();
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if (TID->isPredicable()) {
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for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
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if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
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if (TID->OpInfo[i].isPredicate())
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return i;
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}
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@ -591,7 +591,7 @@ void MachineInstr::copyPredicates(const MachineInstr *MI) {
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const TargetInstrDescriptor *TID = MI->getDesc();
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if (TID->isPredicable()) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
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if (TID->OpInfo[i].isPredicate()) {
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// Predicated operands must be last operands.
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addOperand(MI->getOperand(i));
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}
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@ -296,9 +296,9 @@ static const TargetRegisterClass *getInstrOperandRegClass(
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assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
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return NULL;
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}
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const TargetOperandInfo &toi = II->OpInfo[Op];
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return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS)
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? TII->getPointerRegClass() : MRI->getRegClass(toi.RegClass);
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if (II->OpInfo[Op].isLookupPtrRegClass())
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return TII->getPointerRegClass();
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return MRI->getRegClass(II->OpInfo[Op].RegClass);
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}
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void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
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@ -435,7 +435,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
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unsigned VReg = getVR(Op, VRBaseMap);
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const TargetInstrDescriptor *TID = MI->getDesc();
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bool isOptDef = (IIOpNum < TID->numOperands)
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? (TID->OpInfo[IIOpNum].Flags & M_OPTIONAL_DEF_OPERAND) : false;
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? (TID->OpInfo[IIOpNum].isOptionalDef()) : false;
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MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
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// Verify that it is right.
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@ -38,7 +38,7 @@ bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
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const TargetInstrDescriptor *TID = MI->getDesc();
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if (TID->isPredicable()) {
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for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
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if (TID->OpInfo[i].isPredicate()) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg()) {
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MO.setReg(Pred[j].getReg());
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@ -1882,7 +1882,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
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const TargetInstrDescriptor &TID = get(Opc);
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const TargetOperandInfo &TOI = TID.OpInfo[Index];
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const TargetRegisterClass *RC = (TOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
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const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
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? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
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SmallVector<MachineOperand,4> AddrOps;
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SmallVector<MachineOperand,2> BeforeOps;
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@ -1957,7 +1957,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
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// Emit the store instruction.
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if (UnfoldStore) {
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const TargetOperandInfo &DstTOI = TID.OpInfo[0];
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const TargetRegisterClass *DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
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const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
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? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
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storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
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}
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@ -1981,7 +1981,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
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bool FoldedStore = I->second.second & (1 << 5);
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const TargetInstrDescriptor &TID = get(Opc);
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const TargetOperandInfo &TOI = TID.OpInfo[Index];
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const TargetRegisterClass *RC = (TOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
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const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
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? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
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std::vector<SDOperand> AddrOps;
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std::vector<SDOperand> BeforeOps;
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@ -2013,7 +2013,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
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const TargetRegisterClass *DstRC = 0;
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if (TID.numDefs > 0) {
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const TargetOperandInfo &DstTOI = TID.OpInfo[0];
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DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
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DstRC = DstTOI.isLookupPtrRegClass()
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? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
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VTs.push_back(*DstRC->vt_begin());
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}
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@ -94,17 +94,17 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
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// Ptr value whose register class is resolved via callback.
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if (OpR->getName() == "ptr_rc")
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Res += "|M_LOOK_UP_PTR_REG_CLASS";
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Res += "|TOI::LookupPtrRegClass";
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// Predicate operands. Check to see if the original unexpanded operand
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// was of type PredicateOperand.
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if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
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Res += "|M_PREDICATE_OPERAND";
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Res += "|TOI::Predicate";
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// Optional def operands. Check to see if the original unexpanded operand
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// was of type OptionalDefOperand.
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if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
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Res += "|M_OPTIONAL_DEF_OPERAND";
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Res += "|TOI::OptionalDef";
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// Fill in constraint info.
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Res += ", " + Inst.OperandList[i].Constraints[j];
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