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* Changes to be a MachineFunctionPass
* Frame information is now stuck in MachineFunctionInfo instead of directly in MachineFunction. * Don't require a TM as an argument to the ctor git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5172 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -11,7 +11,8 @@
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#include "SparcInternals.h"
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#include "SparcRegClassInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/InstrSelectionSupport.h"
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@ -19,48 +20,38 @@
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#include "llvm/Function.h"
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namespace {
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class InsertPrologEpilogCode : public FunctionPass {
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TargetMachine &Target;
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public:
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InsertPrologEpilogCode(TargetMachine &T) : Target(T) {}
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struct InsertPrologEpilogCode : public MachineFunctionPass {
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const char *getPassName() const { return "Sparc Prolog/Epilog Inserter"; }
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bool runOnFunction(Function &F) {
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MachineFunction &mcodeInfo = MachineFunction::get(&F);
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if (!mcodeInfo.isCompiledAsLeafMethod()) {
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bool runOnMachineFunction(MachineFunction &F) {
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if (!F.getInfo()->isCompiledAsLeafMethod()) {
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InsertPrologCode(F);
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InsertEpilogCode(F);
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}
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return false;
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}
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void InsertPrologCode(Function &F);
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void InsertEpilogCode(Function &F);
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void InsertPrologCode(MachineFunction &F);
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void InsertEpilogCode(MachineFunction &F);
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};
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} // End anonymous namespace
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//------------------------------------------------------------------------
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// External Function: GetInstructionsForProlog
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// External Function: GetInstructionsForEpilog
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//
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// Purpose:
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// Create prolog and epilog code for procedure entry and exit
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//------------------------------------------------------------------------
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void InsertPrologEpilogCode::InsertPrologCode(Function &F)
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void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
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{
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std::vector<MachineInstr*> mvec;
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MachineInstr* M;
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const MachineFrameInfo& frameInfo = Target.getFrameInfo();
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const TargetMachine &TM = MF.getTarget();
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const TargetFrameInfo& frameInfo = TM.getFrameInfo();
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// The second operand is the stack size. If it does not fit in the
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// immediate field, we have to use a free register to hold the size.
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// See the comments below for the choice of this register.
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//
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MachineFunction& mcInfo = MachineFunction::get(&F);
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unsigned staticStackSize = mcInfo.getStaticStackSize();
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unsigned staticStackSize = MF.getInfo()->getStaticStackSize();
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if (staticStackSize < (unsigned) frameInfo.getMinStackFrameSize())
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staticStackSize = (unsigned) frameInfo.getMinStackFrameSize();
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@ -70,50 +61,50 @@ void InsertPrologEpilogCode::InsertPrologCode(Function &F)
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staticStackSize += frameInfo.getStackFrameSizeAlignment() - padsz;
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int32_t C = - (int) staticStackSize;
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int SP = Target.getRegInfo().getStackPointer();
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if (Target.getInstrInfo().constantFitsInImmedField(SAVE, staticStackSize)) {
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M = BuildMI(SAVE, 3).addMReg(SP).addSImm(C).addMReg(SP);
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mvec.push_back(M);
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int SP = TM.getRegInfo().getStackPointer();
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if (TM.getInstrInfo().constantFitsInImmedField(SAVE, staticStackSize)) {
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mvec.push_back(BuildMI(SAVE, 3).addMReg(SP).addSImm(C).addMReg(SP));
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} else {
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// We have to put the stack size value into a register before SAVE.
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// Use register %g1 since it is volatile across calls. Note that the
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// local (%l) and in (%i) registers cannot be used before the SAVE!
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// Do this by creating a code sequence equivalent to:
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// SETSW -(stackSize), %g1
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int uregNum = Target.getRegInfo().getUnifiedRegNum(
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Target.getRegInfo().getRegClassIDOfType(Type::IntTy),
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SparcIntRegClass::g1);
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M = BuildMI(SETHI, 2).addSImm(C).addMReg(uregNum);
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M->setOperandHi32(0);
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mvec.push_back(M);
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M = BuildMI(OR, 3).addMReg(uregNum).addSImm(C).addMReg(uregNum);
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M->setOperandLo32(1);
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mvec.push_back(M);
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M = BuildMI(SRA, 3).addMReg(uregNum).addZImm(0).addMReg(uregNum);
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mvec.push_back(M);
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// Now generate the SAVE using the value in register %g1
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M = BuildMI(SAVE, 3).addMReg(SP).addMReg(uregNum).addMReg(SP);
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mvec.push_back(M);
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}
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// We have to put the stack size value into a register before SAVE.
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// Use register %g1 since it is volatile across calls. Note that the
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// local (%l) and in (%i) registers cannot be used before the SAVE!
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// Do this by creating a code sequence equivalent to:
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// SETSW -(stackSize), %g1
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int uregNum = TM.getRegInfo().getUnifiedRegNum(
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TM.getRegInfo().getRegClassIDOfType(Type::IntTy),
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SparcIntRegClass::g1);
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MachineBasicBlock& bbMvec = mcInfo.front();
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bbMvec.insert(bbMvec.begin(), mvec.begin(), mvec.end());
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MachineInstr* M = BuildMI(SETHI, 2).addSImm(C).addMReg(uregNum);
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M->setOperandHi32(0);
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mvec.push_back(M);
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M = BuildMI(OR, 3).addMReg(uregNum).addSImm(C).addMReg(uregNum);
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M->setOperandLo32(1);
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mvec.push_back(M);
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M = BuildMI(SRA, 3).addMReg(uregNum).addZImm(0).addMReg(uregNum);
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mvec.push_back(M);
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// Now generate the SAVE using the value in register %g1
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M = BuildMI(SAVE, 3).addMReg(SP).addMReg(uregNum).addMReg(SP);
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mvec.push_back(M);
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}
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MF.front().insert(MF.front().begin(), mvec.begin(), mvec.end());
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}
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void InsertPrologEpilogCode::InsertEpilogCode(Function &F)
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void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF)
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{
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MachineFunction &MF = MachineFunction::get(&F);
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const TargetMachine &TM = MF.getTarget();
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const MachineInstrInfo &MII = TM.getInstrInfo();
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
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MachineBasicBlock &MBB = *I;
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BasicBlock &BB = *I->getBasicBlock();
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Instruction *TermInst = (Instruction*)BB.getTerminator();
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if (TermInst->getOpcode() == Instruction::Ret)
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{
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int ZR = Target.getRegInfo().getZeroRegNum();
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int ZR = TM.getRegInfo().getZeroRegNum();
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MachineInstr *Restore =
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BuildMI(RESTORE, 3).addMReg(ZR).addSImm(0).addMReg(ZR);
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@ -121,7 +112,6 @@ void InsertPrologEpilogCode::InsertEpilogCode(Function &F)
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MachineCodeForInstruction::get(TermInst);
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// Remove the NOPs in the delay slots of the return instruction
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const MachineInstrInfo &mii = Target.getInstrInfo();
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unsigned numNOPs = 0;
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while (termMvec.back()->getOpCode() == NOP)
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{
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@ -134,7 +124,7 @@ void InsertPrologEpilogCode::InsertEpilogCode(Function &F)
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// Check that we found the right number of NOPs and have the right
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// number of instructions to replace them.
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unsigned ndelays = mii.getNumDelaySlots(termMvec.back()->getOpCode());
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unsigned ndelays = MII.getNumDelaySlots(termMvec.back()->getOpCode());
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assert(numNOPs == ndelays && "Missing NOPs in delay slots?");
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assert(ndelays == 1 && "Cannot use epilog code for delay slots?");
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@ -145,5 +135,5 @@ void InsertPrologEpilogCode::InsertEpilogCode(Function &F)
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}
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Pass* UltraSparc::getPrologEpilogInsertionPass() {
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return new InsertPrologEpilogCode(*this);
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return new InsertPrologEpilogCode();
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}
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