mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
[ms-inline asm] Refactor. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179610 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
parent
7e5d54c320
commit
8ccacf788a
@ -33,11 +33,403 @@ using namespace llvm;
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namespace {
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struct X86Operand;
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static const char OpPrecedence[] = {
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0, // IC_PLUS
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0, // IC_MINUS
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1, // IC_MULTIPLY
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1, // IC_DIVIDE
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2, // IC_RPAREN
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3, // IC_LPAREN
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0, // IC_IMM
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0 // IC_REGISTER
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};
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class X86AsmParser : public MCTargetAsmParser {
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MCSubtargetInfo &STI;
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MCAsmParser &Parser;
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ParseInstructionInfo *InstInfo;
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private:
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enum InfixCalculatorTok {
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IC_PLUS = 0,
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IC_MINUS,
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IC_MULTIPLY,
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IC_DIVIDE,
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IC_RPAREN,
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IC_LPAREN,
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IC_IMM,
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IC_REGISTER
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};
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class InfixCalculator {
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typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
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SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
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SmallVector<ICToken, 4> PostfixStack;
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public:
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int64_t popOperand() {
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assert (!PostfixStack.empty() && "Poped an empty stack!");
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ICToken Op = PostfixStack.pop_back_val();
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assert ((Op.first == IC_IMM || Op.first == IC_REGISTER)
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&& "Expected and immediate or register!");
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return Op.second;
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}
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void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
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assert ((Op == IC_IMM || Op == IC_REGISTER) &&
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"Unexpected operand!");
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PostfixStack.push_back(std::make_pair(Op, Val));
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}
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void popOperator() { InfixOperatorStack.pop_back_val(); }
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void pushOperator(InfixCalculatorTok Op) {
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// Push the new operator if the stack is empty.
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if (InfixOperatorStack.empty()) {
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InfixOperatorStack.push_back(Op);
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return;
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}
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// Push the new operator if it has a higher precedence than the operator
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// on the top of the stack or the operator on the top of the stack is a
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// left parentheses.
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unsigned Idx = InfixOperatorStack.size() - 1;
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InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
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if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
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InfixOperatorStack.push_back(Op);
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return;
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}
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// The operator on the top of the stack has higher precedence than the
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// new operator.
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unsigned ParenCount = 0;
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while (1) {
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// Nothing to process.
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if (InfixOperatorStack.empty())
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break;
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Idx = InfixOperatorStack.size() - 1;
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StackOp = InfixOperatorStack[Idx];
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if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
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break;
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// If we have an even parentheses count and we see a left parentheses,
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// then stop processing.
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if (!ParenCount && StackOp == IC_LPAREN)
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break;
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if (StackOp == IC_RPAREN) {
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++ParenCount;
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InfixOperatorStack.pop_back_val();
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} else if (StackOp == IC_LPAREN) {
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--ParenCount;
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InfixOperatorStack.pop_back_val();
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} else {
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InfixOperatorStack.pop_back_val();
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PostfixStack.push_back(std::make_pair(StackOp, 0));
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}
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}
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// Push the new operator.
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InfixOperatorStack.push_back(Op);
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}
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int64_t execute() {
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// Push any remaining operators onto the postfix stack.
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while (!InfixOperatorStack.empty()) {
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InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
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if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
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PostfixStack.push_back(std::make_pair(StackOp, 0));
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}
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if (PostfixStack.empty())
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return 0;
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SmallVector<ICToken, 16> OperandStack;
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for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
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ICToken Op = PostfixStack[i];
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if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
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OperandStack.push_back(Op);
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} else {
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assert (OperandStack.size() > 1 && "Too few operands.");
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int64_t Val;
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ICToken Op2 = OperandStack.pop_back_val();
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ICToken Op1 = OperandStack.pop_back_val();
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switch (Op.first) {
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default:
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report_fatal_error("Unexpected operator!");
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break;
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case IC_PLUS:
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Val = Op1.second + Op2.second;
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OperandStack.push_back(std::make_pair(IC_IMM, Val));
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break;
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case IC_MINUS:
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Val = Op1.second - Op2.second;
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OperandStack.push_back(std::make_pair(IC_IMM, Val));
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break;
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case IC_MULTIPLY:
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assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
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"Multiply operation with an immediate and a register!");
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Val = Op1.second * Op2.second;
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OperandStack.push_back(std::make_pair(IC_IMM, Val));
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break;
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case IC_DIVIDE:
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assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
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"Divide operation with an immediate and a register!");
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assert (Op2.second != 0 && "Division by zero!");
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Val = Op1.second / Op2.second;
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OperandStack.push_back(std::make_pair(IC_IMM, Val));
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break;
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}
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}
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}
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assert (OperandStack.size() == 1 && "Expected a single result.");
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return OperandStack.pop_back_val().second;
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}
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};
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enum IntelExprState {
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IES_PLUS,
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IES_MINUS,
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IES_MULTIPLY,
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IES_DIVIDE,
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IES_LBRAC,
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IES_RBRAC,
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IES_LPAREN,
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IES_RPAREN,
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IES_REGISTER,
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IES_REGISTER_STAR,
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IES_INTEGER,
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IES_INTEGER_STAR,
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IES_IDENTIFIER,
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IES_ERROR
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};
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class IntelExprStateMachine {
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IntelExprState State;
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unsigned BaseReg, IndexReg, TmpReg, Scale;
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int64_t Disp;
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const MCExpr *Sym;
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StringRef SymName;
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InfixCalculator IC;
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public:
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IntelExprStateMachine(int64_t disp) :
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State(IES_PLUS), BaseReg(0), IndexReg(0), TmpReg(0), Scale(1), Disp(disp),
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Sym(0) {}
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unsigned getBaseReg() { return BaseReg; }
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unsigned getIndexReg() { return IndexReg; }
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unsigned getScale() { return Scale; }
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const MCExpr *getSym() { return Sym; }
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StringRef getSymName() { return SymName; }
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int64_t getImm() { return Disp + IC.execute(); }
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bool isValidEndState() { return State == IES_RBRAC; }
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void onPlus() {
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switch (State) {
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default:
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State = IES_ERROR;
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break;
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case IES_INTEGER:
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case IES_RPAREN:
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State = IES_PLUS;
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IC.pushOperator(IC_PLUS);
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break;
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case IES_REGISTER:
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State = IES_PLUS;
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// If we already have a BaseReg, then assume this is the IndexReg with a
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// scale of 1.
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if (!BaseReg) {
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BaseReg = TmpReg;
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} else {
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assert (!IndexReg && "BaseReg/IndexReg already set!");
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IndexReg = TmpReg;
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Scale = 1;
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}
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IC.pushOperator(IC_PLUS);
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break;
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}
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}
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void onMinus() {
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switch (State) {
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default:
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State = IES_ERROR;
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break;
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case IES_PLUS:
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case IES_LPAREN:
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IC.pushOperand(IC_IMM);
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case IES_INTEGER:
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case IES_RPAREN:
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State = IES_MINUS;
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IC.pushOperator(IC_MINUS);
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break;
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case IES_REGISTER:
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State = IES_MINUS;
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// If we already have a BaseReg, then assume this is the IndexReg with a
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// scale of 1.
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if (!BaseReg) {
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BaseReg = TmpReg;
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} else {
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assert (!IndexReg && "BaseReg/IndexReg already set!");
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IndexReg = TmpReg;
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Scale = 1;
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}
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IC.pushOperator(IC_MINUS);
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break;
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}
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}
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void onRegister(unsigned Reg) {
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switch (State) {
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default:
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State = IES_ERROR;
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break;
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case IES_PLUS:
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case IES_LPAREN:
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State = IES_REGISTER;
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TmpReg = Reg;
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IC.pushOperand(IC_REGISTER);
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break;
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case IES_INTEGER_STAR:
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assert (!IndexReg && "IndexReg already set!");
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State = IES_INTEGER;
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IndexReg = Reg;
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Scale = IC.popOperand();
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IC.pushOperand(IC_IMM);
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IC.popOperator();
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break;
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}
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}
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void onDispExpr(const MCExpr *SymRef, StringRef SymRefName) {
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switch (State) {
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default:
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State = IES_ERROR;
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break;
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case IES_PLUS:
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case IES_MINUS:
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State = IES_INTEGER;
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Sym = SymRef;
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SymName = SymRefName;
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IC.pushOperand(IC_IMM);
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break;
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}
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}
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void onInteger(int64_t TmpInt) {
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switch (State) {
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default:
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State = IES_ERROR;
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break;
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case IES_PLUS:
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case IES_MINUS:
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case IES_MULTIPLY:
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case IES_DIVIDE:
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case IES_LPAREN:
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case IES_INTEGER_STAR:
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State = IES_INTEGER;
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IC.pushOperand(IC_IMM, TmpInt);
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break;
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case IES_REGISTER_STAR:
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assert (!IndexReg && "IndexReg already set!");
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State = IES_INTEGER;
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IndexReg = TmpReg;
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Scale = TmpInt;
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IC.popOperator();
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break;
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}
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}
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void onStar() {
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switch (State) {
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default:
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State = IES_ERROR;
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break;
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case IES_INTEGER:
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State = IES_INTEGER_STAR;
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IC.pushOperator(IC_MULTIPLY);
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break;
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case IES_REGISTER:
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State = IES_REGISTER_STAR;
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IC.pushOperator(IC_MULTIPLY);
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break;
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case IES_RPAREN:
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State = IES_MULTIPLY;
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IC.pushOperator(IC_MULTIPLY);
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break;
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}
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}
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void onDivide() {
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switch (State) {
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default:
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State = IES_ERROR;
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break;
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case IES_INTEGER:
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State = IES_DIVIDE;
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IC.pushOperator(IC_DIVIDE);
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break;
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}
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}
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void onLBrac() {
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switch (State) {
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default:
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State = IES_ERROR;
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break;
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case IES_RBRAC:
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State = IES_PLUS;
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IC.pushOperator(IC_PLUS);
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break;
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}
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}
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void onRBrac() {
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switch (State) {
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default:
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State = IES_ERROR;
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break;
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case IES_RPAREN:
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case IES_INTEGER:
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State = IES_RBRAC;
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break;
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case IES_REGISTER:
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State = IES_RBRAC;
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// If we already have a BaseReg, then assume this is the IndexReg with a
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// scale of 1.
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if (!BaseReg) {
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BaseReg = TmpReg;
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} else {
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assert (!IndexReg && "BaseReg/IndexReg already set!");
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IndexReg = TmpReg;
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Scale = 1;
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}
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break;
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}
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}
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void onLParen() {
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switch (State) {
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default:
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State = IES_ERROR;
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break;
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case IES_PLUS:
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case IES_MINUS:
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case IES_MULTIPLY:
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case IES_DIVIDE:
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case IES_INTEGER_STAR:
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case IES_LPAREN:
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State = IES_LPAREN;
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IC.pushOperator(IC_LPAREN);
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break;
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}
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}
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void onRParen() {
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switch (State) {
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default:
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State = IES_ERROR;
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break;
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case IES_REGISTER:
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case IES_INTEGER:
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case IES_PLUS:
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case IES_MINUS:
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case IES_MULTIPLY:
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case IES_DIVIDE:
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case IES_RPAREN:
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State = IES_RPAREN;
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IC.pushOperator(IC_RPAREN);
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break;
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}
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}
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};
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MCAsmParser &getParser() const { return Parser; }
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MCAsmLexer &getLexer() const { return Parser.getLexer(); }
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@ -61,6 +453,7 @@ private:
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X86Operand *ParseIntelOperator(unsigned OpKind);
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X86Operand *ParseIntelMemOperand(unsigned SegReg, uint64_t ImmDisp,
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SMLoc StartLoc);
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X86Operand *ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
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X86Operand *ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
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uint64_t ImmDisp, unsigned Size);
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X86Operand *ParseIntelVarWithQualifier(const MCExpr *&Disp,
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@ -687,397 +1080,6 @@ static unsigned getIntelMemOperandSize(StringRef OpStr) {
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return Size;
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}
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enum InfixCalculatorTok {
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IC_PLUS = 0,
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IC_MINUS,
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IC_MULTIPLY,
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IC_DIVIDE,
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IC_RPAREN,
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IC_LPAREN,
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IC_IMM,
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IC_REGISTER
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};
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static const char OpPrecedence[] = {
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0, // IC_PLUS
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0, // IC_MINUS
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1, // IC_MULTIPLY
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1, // IC_DIVIDE
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2, // IC_RPAREN
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3, // IC_LPAREN
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0, // IC_IMM
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0 // IC_REGISTER
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};
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class InfixCalculator {
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typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
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SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
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SmallVector<ICToken, 4> PostfixStack;
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public:
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int64_t popOperand() {
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assert (!PostfixStack.empty() && "Poped an empty stack!");
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ICToken Op = PostfixStack.pop_back_val();
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assert ((Op.first == IC_IMM || Op.first == IC_REGISTER)
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&& "Expected and immediate or register!");
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return Op.second;
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}
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void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
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assert ((Op == IC_IMM || Op == IC_REGISTER) &&
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"Unexpected operand!");
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PostfixStack.push_back(std::make_pair(Op, Val));
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}
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void popOperator() { InfixOperatorStack.pop_back_val(); }
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void pushOperator(InfixCalculatorTok Op) {
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// Push the new operator if the stack is empty.
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if (InfixOperatorStack.empty()) {
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InfixOperatorStack.push_back(Op);
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return;
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}
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// Push the new operator if it has a higher precedence than the operator on
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// the top of the stack or the operator on the top of the stack is a left
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// parentheses.
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unsigned Idx = InfixOperatorStack.size() - 1;
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InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
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if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
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InfixOperatorStack.push_back(Op);
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return;
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}
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// The operator on the top of the stack has higher precedence than the
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// new operator.
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unsigned ParenCount = 0;
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while (1) {
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// Nothing to process.
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if (InfixOperatorStack.empty())
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break;
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Idx = InfixOperatorStack.size() - 1;
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StackOp = InfixOperatorStack[Idx];
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if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
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break;
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// If we have an even parentheses count and we see a left parentheses,
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// then stop processing.
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if (!ParenCount && StackOp == IC_LPAREN)
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break;
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if (StackOp == IC_RPAREN) {
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||||
++ParenCount;
|
||||
InfixOperatorStack.pop_back_val();
|
||||
} else if (StackOp == IC_LPAREN) {
|
||||
--ParenCount;
|
||||
InfixOperatorStack.pop_back_val();
|
||||
} else {
|
||||
InfixOperatorStack.pop_back_val();
|
||||
PostfixStack.push_back(std::make_pair(StackOp, 0));
|
||||
}
|
||||
}
|
||||
// Push the new operator.
|
||||
InfixOperatorStack.push_back(Op);
|
||||
}
|
||||
int64_t execute() {
|
||||
// Push any remaining operators onto the postfix stack.
|
||||
while (!InfixOperatorStack.empty()) {
|
||||
InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
|
||||
if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
|
||||
PostfixStack.push_back(std::make_pair(StackOp, 0));
|
||||
}
|
||||
|
||||
if (PostfixStack.empty())
|
||||
return 0;
|
||||
|
||||
SmallVector<ICToken, 16> OperandStack;
|
||||
for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
|
||||
ICToken Op = PostfixStack[i];
|
||||
if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
|
||||
OperandStack.push_back(Op);
|
||||
} else {
|
||||
assert (OperandStack.size() > 1 && "Too few operands.");
|
||||
int64_t Val;
|
||||
ICToken Op2 = OperandStack.pop_back_val();
|
||||
ICToken Op1 = OperandStack.pop_back_val();
|
||||
switch (Op.first) {
|
||||
default:
|
||||
report_fatal_error("Unexpected operator!");
|
||||
break;
|
||||
case IC_PLUS:
|
||||
Val = Op1.second + Op2.second;
|
||||
OperandStack.push_back(std::make_pair(IC_IMM, Val));
|
||||
break;
|
||||
case IC_MINUS:
|
||||
Val = Op1.second - Op2.second;
|
||||
OperandStack.push_back(std::make_pair(IC_IMM, Val));
|
||||
break;
|
||||
case IC_MULTIPLY:
|
||||
assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
|
||||
"Multiply operation with an immediate and a register!");
|
||||
Val = Op1.second * Op2.second;
|
||||
OperandStack.push_back(std::make_pair(IC_IMM, Val));
|
||||
break;
|
||||
case IC_DIVIDE:
|
||||
assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
|
||||
"Divide operation with an immediate and a register!");
|
||||
assert (Op2.second != 0 && "Division by zero!");
|
||||
Val = Op1.second / Op2.second;
|
||||
OperandStack.push_back(std::make_pair(IC_IMM, Val));
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
assert (OperandStack.size() == 1 && "Expected a single result.");
|
||||
return OperandStack.pop_back_val().second;
|
||||
}
|
||||
};
|
||||
|
||||
enum IntelBracExprState {
|
||||
IBES_PLUS,
|
||||
IBES_MINUS,
|
||||
IBES_MULTIPLY,
|
||||
IBES_DIVIDE,
|
||||
IBES_LBRAC,
|
||||
IBES_RBRAC,
|
||||
IBES_LPAREN,
|
||||
IBES_RPAREN,
|
||||
IBES_REGISTER,
|
||||
IBES_REGISTER_STAR,
|
||||
IBES_INTEGER,
|
||||
IBES_INTEGER_STAR,
|
||||
IBES_IDENTIFIER,
|
||||
IBES_ERROR
|
||||
};
|
||||
|
||||
class IntelBracExprStateMachine {
|
||||
IntelBracExprState State;
|
||||
unsigned BaseReg, IndexReg, TmpReg, Scale;
|
||||
int64_t Disp;
|
||||
const MCExpr *Sym;
|
||||
StringRef SymName;
|
||||
InfixCalculator IC;
|
||||
public:
|
||||
IntelBracExprStateMachine(MCAsmParser &parser, int64_t disp) :
|
||||
State(IBES_PLUS), BaseReg(0), IndexReg(0), TmpReg(0), Scale(1), Disp(disp),
|
||||
Sym(0) {}
|
||||
|
||||
unsigned getBaseReg() { return BaseReg; }
|
||||
unsigned getIndexReg() { return IndexReg; }
|
||||
unsigned getScale() { return Scale; }
|
||||
const MCExpr *getSym() { return Sym; }
|
||||
StringRef getSymName() { return SymName; }
|
||||
int64_t getImmDisp() { return Disp + IC.execute(); }
|
||||
bool isValidEndState() { return State == IBES_RBRAC; }
|
||||
|
||||
void onPlus() {
|
||||
switch (State) {
|
||||
default:
|
||||
State = IBES_ERROR;
|
||||
break;
|
||||
case IBES_INTEGER:
|
||||
case IBES_RPAREN:
|
||||
State = IBES_PLUS;
|
||||
IC.pushOperator(IC_PLUS);
|
||||
break;
|
||||
case IBES_REGISTER:
|
||||
State = IBES_PLUS;
|
||||
// If we already have a BaseReg, then assume this is the IndexReg with a
|
||||
// scale of 1.
|
||||
if (!BaseReg) {
|
||||
BaseReg = TmpReg;
|
||||
} else {
|
||||
assert (!IndexReg && "BaseReg/IndexReg already set!");
|
||||
IndexReg = TmpReg;
|
||||
Scale = 1;
|
||||
}
|
||||
IC.pushOperator(IC_PLUS);
|
||||
break;
|
||||
}
|
||||
}
|
||||
void onMinus() {
|
||||
switch (State) {
|
||||
default:
|
||||
State = IBES_ERROR;
|
||||
break;
|
||||
case IBES_PLUS:
|
||||
case IBES_LPAREN:
|
||||
IC.pushOperand(IC_IMM);
|
||||
case IBES_INTEGER:
|
||||
case IBES_RPAREN:
|
||||
State = IBES_MINUS;
|
||||
IC.pushOperator(IC_MINUS);
|
||||
break;
|
||||
case IBES_REGISTER:
|
||||
State = IBES_MINUS;
|
||||
// If we already have a BaseReg, then assume this is the IndexReg with a
|
||||
// scale of 1.
|
||||
if (!BaseReg) {
|
||||
BaseReg = TmpReg;
|
||||
} else {
|
||||
assert (!IndexReg && "BaseReg/IndexReg already set!");
|
||||
IndexReg = TmpReg;
|
||||
Scale = 1;
|
||||
}
|
||||
IC.pushOperator(IC_MINUS);
|
||||
break;
|
||||
}
|
||||
}
|
||||
void onRegister(unsigned Reg) {
|
||||
switch (State) {
|
||||
default:
|
||||
State = IBES_ERROR;
|
||||
break;
|
||||
case IBES_PLUS:
|
||||
case IBES_LPAREN:
|
||||
State = IBES_REGISTER;
|
||||
TmpReg = Reg;
|
||||
IC.pushOperand(IC_REGISTER);
|
||||
break;
|
||||
case IBES_INTEGER_STAR:
|
||||
assert (!IndexReg && "IndexReg already set!");
|
||||
State = IBES_INTEGER;
|
||||
IndexReg = Reg;
|
||||
Scale = IC.popOperand();
|
||||
IC.pushOperand(IC_IMM);
|
||||
IC.popOperator();
|
||||
break;
|
||||
}
|
||||
}
|
||||
void onDispExpr(const MCExpr *SymRef, StringRef SymRefName) {
|
||||
switch (State) {
|
||||
default:
|
||||
State = IBES_ERROR;
|
||||
break;
|
||||
case IBES_PLUS:
|
||||
case IBES_MINUS:
|
||||
State = IBES_INTEGER;
|
||||
Sym = SymRef;
|
||||
SymName = SymRefName;
|
||||
IC.pushOperand(IC_IMM);
|
||||
break;
|
||||
}
|
||||
}
|
||||
void onInteger(int64_t TmpInt) {
|
||||
switch (State) {
|
||||
default:
|
||||
State = IBES_ERROR;
|
||||
break;
|
||||
case IBES_PLUS:
|
||||
case IBES_MINUS:
|
||||
case IBES_MULTIPLY:
|
||||
case IBES_DIVIDE:
|
||||
case IBES_LPAREN:
|
||||
case IBES_INTEGER_STAR:
|
||||
State = IBES_INTEGER;
|
||||
IC.pushOperand(IC_IMM, TmpInt);
|
||||
break;
|
||||
case IBES_REGISTER_STAR:
|
||||
assert (!IndexReg && "IndexReg already set!");
|
||||
State = IBES_INTEGER;
|
||||
IndexReg = TmpReg;
|
||||
Scale = TmpInt;
|
||||
IC.popOperator();
|
||||
break;
|
||||
}
|
||||
}
|
||||
void onStar() {
|
||||
switch (State) {
|
||||
default:
|
||||
State = IBES_ERROR;
|
||||
break;
|
||||
case IBES_INTEGER:
|
||||
State = IBES_INTEGER_STAR;
|
||||
IC.pushOperator(IC_MULTIPLY);
|
||||
break;
|
||||
case IBES_REGISTER:
|
||||
State = IBES_REGISTER_STAR;
|
||||
IC.pushOperator(IC_MULTIPLY);
|
||||
break;
|
||||
case IBES_RPAREN:
|
||||
State = IBES_MULTIPLY;
|
||||
IC.pushOperator(IC_MULTIPLY);
|
||||
break;
|
||||
}
|
||||
}
|
||||
void onDivide() {
|
||||
switch (State) {
|
||||
default:
|
||||
State = IBES_ERROR;
|
||||
break;
|
||||
case IBES_INTEGER:
|
||||
State = IBES_DIVIDE;
|
||||
IC.pushOperator(IC_DIVIDE);
|
||||
break;
|
||||
}
|
||||
}
|
||||
void onLBrac() {
|
||||
switch (State) {
|
||||
default:
|
||||
State = IBES_ERROR;
|
||||
break;
|
||||
case IBES_RBRAC:
|
||||
State = IBES_PLUS;
|
||||
IC.pushOperator(IC_PLUS);
|
||||
break;
|
||||
}
|
||||
}
|
||||
void onRBrac() {
|
||||
switch (State) {
|
||||
default:
|
||||
State = IBES_ERROR;
|
||||
break;
|
||||
case IBES_RPAREN:
|
||||
case IBES_INTEGER:
|
||||
State = IBES_RBRAC;
|
||||
break;
|
||||
case IBES_REGISTER:
|
||||
State = IBES_RBRAC;
|
||||
// If we already have a BaseReg, then assume this is the IndexReg with a
|
||||
// scale of 1.
|
||||
if (!BaseReg) {
|
||||
BaseReg = TmpReg;
|
||||
} else {
|
||||
assert (!IndexReg && "BaseReg/IndexReg already set!");
|
||||
IndexReg = TmpReg;
|
||||
Scale = 1;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
void onLParen() {
|
||||
switch (State) {
|
||||
default:
|
||||
State = IBES_ERROR;
|
||||
break;
|
||||
case IBES_PLUS:
|
||||
case IBES_MINUS:
|
||||
case IBES_MULTIPLY:
|
||||
case IBES_DIVIDE:
|
||||
case IBES_INTEGER_STAR:
|
||||
case IBES_LPAREN:
|
||||
State = IBES_LPAREN;
|
||||
IC.pushOperator(IC_LPAREN);
|
||||
break;
|
||||
}
|
||||
}
|
||||
void onRParen() {
|
||||
switch (State) {
|
||||
default:
|
||||
State = IBES_ERROR;
|
||||
break;
|
||||
case IBES_REGISTER:
|
||||
case IBES_INTEGER:
|
||||
case IBES_PLUS:
|
||||
case IBES_MINUS:
|
||||
case IBES_MULTIPLY:
|
||||
case IBES_DIVIDE:
|
||||
case IBES_RPAREN:
|
||||
State = IBES_RPAREN;
|
||||
IC.pushOperator(IC_RPAREN);
|
||||
break;
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
X86Operand *
|
||||
X86AsmParser::CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp,
|
||||
unsigned BaseReg, unsigned IndexReg,
|
||||
@ -1182,21 +1184,11 @@ RewriteIntelBracExpression(SmallVectorImpl<AsmRewrite> *AsmRewrites,
|
||||
}
|
||||
}
|
||||
|
||||
X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
|
||||
uint64_t ImmDisp,
|
||||
unsigned Size) {
|
||||
X86Operand *
|
||||
X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
|
||||
const AsmToken &Tok = Parser.getTok();
|
||||
SMLoc BracLoc = Tok.getLoc(), End = Tok.getEndLoc();
|
||||
if (getLexer().isNot(AsmToken::LBrac))
|
||||
return ErrorOperand(BracLoc, "Expected '[' token!");
|
||||
Parser.Lex(); // Eat '['
|
||||
|
||||
SMLoc StartInBrac = Tok.getLoc();
|
||||
// Parse [ Symbol + ImmDisp ] and [ BaseReg + Scale*IndexReg + ImmDisp ]. We
|
||||
// may have already parsed an immediate displacement before the bracketed
|
||||
// expression.
|
||||
bool Done = false;
|
||||
IntelBracExprStateMachine SM(Parser, ImmDisp);
|
||||
while (!Done) {
|
||||
bool UpdateLocLex = true;
|
||||
|
||||
@ -1253,6 +1245,28 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
|
||||
Parser.Lex(); // Consume the token.
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
|
||||
uint64_t ImmDisp,
|
||||
unsigned Size) {
|
||||
const AsmToken &Tok = Parser.getTok();
|
||||
SMLoc BracLoc = Tok.getLoc(), End = Tok.getEndLoc();
|
||||
if (getLexer().isNot(AsmToken::LBrac))
|
||||
return ErrorOperand(BracLoc, "Expected '[' token!");
|
||||
Parser.Lex(); // Eat '['
|
||||
|
||||
SMLoc StartInBrac = Tok.getLoc();
|
||||
// Parse [ Symbol + ImmDisp ] and [ BaseReg + Scale*IndexReg + ImmDisp ]. We
|
||||
// may have already parsed an immediate displacement before the bracketed
|
||||
// expression.
|
||||
|
||||
StringRef SymName;
|
||||
|
||||
IntelExprStateMachine SM(ImmDisp);
|
||||
if (X86Operand *Err = ParseIntelExpression(SM, End))
|
||||
return Err;
|
||||
|
||||
const MCExpr *Disp;
|
||||
if (const MCExpr *Sym = SM.getSym()) {
|
||||
@ -1260,11 +1274,11 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
|
||||
Disp = Sym;
|
||||
if (isParsingInlineAsm())
|
||||
RewriteIntelBracExpression(InstInfo->AsmRewrites, SM.getSymName(),
|
||||
ImmDisp, SM.getImmDisp(), BracLoc, StartInBrac,
|
||||
ImmDisp, SM.getImm(), BracLoc, StartInBrac,
|
||||
End);
|
||||
} else {
|
||||
// An immediate displacement only.
|
||||
Disp = MCConstantExpr::Create(SM.getImmDisp(), getContext());
|
||||
Disp = MCConstantExpr::Create(SM.getImm(), getContext());
|
||||
}
|
||||
|
||||
// Parse the dot operator (e.g., [ebx].foo.bar).
|
||||
|
||||
Loading…
Reference in New Issue
Block a user