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Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83598 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2009-10-08 23:51:31 +00:00
parent c5c6edb74f
commit 8cdb269686
4 changed files with 105 additions and 13 deletions
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58
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -1967,18 +1967,58 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
SDValue MemAddr, MemUpdate, MemOpc;
if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
return NULL;
switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
VT = N->getOperand(3).getValueType();
if (VT.is64BitVector()) {
switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled vst3lane type");
case MVT::v8i8: Opc = ARM::VST3LNd8; break;
case MVT::v4i16: Opc = ARM::VST3LNd16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VST3LNd32; break;
}
SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(3), N->getOperand(4),
N->getOperand(5), N->getOperand(6), Chain };
return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8);
}
// Quad registers are handled by extracting subregs and then doing
// the store.
EVT RegVT;
unsigned Opc2 = 0;
switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled vst3lane type");
case MVT::v8i8: Opc = ARM::VST3LNd8; break;
case MVT::v4i16: Opc = ARM::VST3LNd16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VST3LNd32; break;
case MVT::v8i16:
Opc = ARM::VST3LNq16a;
Opc2 = ARM::VST3LNq16b;
RegVT = MVT::v4i16;
break;
case MVT::v4f32:
Opc = ARM::VST3LNq32a;
Opc2 = ARM::VST3LNq32b;
RegVT = MVT::v2f32;
break;
case MVT::v4i32:
Opc = ARM::VST3LNq32a;
Opc2 = ARM::VST3LNq32b;
RegVT = MVT::v2i32;
break;
}
SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(3), N->getOperand(4),
N->getOperand(5), N->getOperand(6), Chain };
return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8);
unsigned Lane = cast<ConstantSDNode>(N->getOperand(6))->getZExtValue();
unsigned NumElts = RegVT.getVectorNumElements();
int SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
SDValue D0 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
N->getOperand(3));
SDValue D1 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
N->getOperand(4));
SDValue D2 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
N->getOperand(5));
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, D0, D1, D2,
getI32Imm(Lane % NumElts), Chain };
return CurDAG->getMachineNode((Lane < NumElts) ? Opc : Opc2,
dl, MVT::Other, Ops, 8);
}
case Intrinsic::arm_neon_vst4lane: {

16
lib/Target/ARM/ARMInstrNEON.td
View File

@ -469,16 +469,24 @@ def VST2LNq16b: VST2LN<0b0100, "vst2.16">;
def VST2LNq32b: VST2LN<0b1000, "vst2.32">;
// VST3LN : Vector Store (single 3-element structure from one lane)
class VST3LND<bits<4> op11_8, string OpcodeStr>
class VST3LN<bits<4> op11_8, string OpcodeStr>
: NLdSt<1,0b00,op11_8,0b0000, (outs),
(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
nohash_imm:$lane), IIC_VST,
!strconcat(OpcodeStr,
"\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), "", []>;
def VST3LNd8 : VST3LND<0b0010, "vst3.8">;
def VST3LNd16 : VST3LND<0b0110, "vst3.16">;
def VST3LNd32 : VST3LND<0b1010, "vst3.32">;
def VST3LNd8 : VST3LN<0b0010, "vst3.8">;
def VST3LNd16 : VST3LN<0b0110, "vst3.16">;
def VST3LNd32 : VST3LN<0b1010, "vst3.32">;
// vst3 to double-spaced even registers.
def VST3LNq16a: VST3LN<0b0110, "vst3.16">;
def VST3LNq32a: VST3LN<0b1010, "vst3.32">;
// vst3 to double-spaced odd registers.
def VST3LNq16b: VST3LN<0b0110, "vst3.16">;
def VST3LNq32b: VST3LN<0b1010, "vst3.32">;
// VST4LN : Vector Store (single 4-element structure from one lane)
class VST4LND<bits<4> op11_8, string OpcodeStr>

16
lib/Target/ARM/NEONPreAllocPass.cpp
View File

@ -233,6 +233,22 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
Stride = 2;
return true;
case ARM::VST3LNq16a:
case ARM::VST3LNq32a:
FirstOpnd = 3;
NumRegs = 3;
Offset = 0;
Stride = 2;
return true;
case ARM::VST3LNq16b:
case ARM::VST3LNq32b:
FirstOpnd = 3;
NumRegs = 3;
Offset = 1;
Stride = 2;
return true;
case ARM::VST4d8:
case ARM::VST4d16:
case ARM::VST4d32:

28
test/CodeGen/ARM/vstlane.ll
View File

@ -97,11 +97,39 @@ define void @vst3lanef(float* %A, <2 x float>* %B) nounwind {
ret void
}
define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
;CHECK: vst3laneQi16:
;CHECK: vst3.16
%tmp1 = load <8 x i16>* %B
call void @llvm.arm.neon.vst3lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 6)
ret void
}
define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
;CHECK: vst3laneQi32:
;CHECK: vst3.32
%tmp1 = load <4 x i32>* %B
call void @llvm.arm.neon.vst3lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0)
ret void
}
define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind {
;CHECK: vst3laneQf:
;CHECK: vst3.32
%tmp1 = load <4 x float>* %B
call void @llvm.arm.neon.vst3lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
ret void
}
declare void @llvm.arm.neon.vst3lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind
declare void @llvm.arm.neon.vst3lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind
declare void @llvm.arm.neon.vst3lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
declare void @llvm.arm.neon.vst3lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32) nounwind
declare void @llvm.arm.neon.vst3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32) nounwind
declare void @llvm.arm.neon.vst3lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind
declare void @llvm.arm.neon.vst3lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32) nounwind
define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
;CHECK: vst4lanei8: