mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-27 02:31:09 +00:00
Lower setcc branchless, if this is profitable.
Based on the patch by Brian Lucas! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91175 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
c42a0b75a4
commit
8d1ffbd1ad
@ -115,8 +115,8 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
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setOperationAction(ISD::BR_CC, MVT::i8, Custom);
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setOperationAction(ISD::BR_CC, MVT::i16, Custom);
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::SETCC, MVT::i8, Expand);
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setOperationAction(ISD::SETCC, MVT::i16, Expand);
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setOperationAction(ISD::SETCC, MVT::i8, Custom);
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setOperationAction(ISD::SETCC, MVT::i16, Custom);
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setOperationAction(ISD::SELECT, MVT::i8, Expand);
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setOperationAction(ISD::SELECT, MVT::i16, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
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@ -183,6 +183,7 @@ SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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case ISD::SRA: return LowerShifts(Op, DAG);
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case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
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case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
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case ISD::SETCC: return LowerSETCC(Op, DAG);
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case ISD::BR_CC: return LowerBR_CC(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
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@ -701,6 +702,88 @@ SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
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Chain, Dest, TargetCC, Flag);
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}
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SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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DebugLoc dl = Op.getDebugLoc();
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// If we are doing an AND and testing against zero, then the CMP
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// will not be generated. The AND (or BIT) will generate the condition codes,
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// but they are different from CMP.
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bool andCC = false;
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if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
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if (RHSC->isNullValue() && LHS.hasOneUse() &&
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(LHS.getOpcode() == ISD::AND ||
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(LHS.getOpcode() == ISD::TRUNCATE &&
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LHS.getOperand(0).getOpcode() == ISD::AND))) {
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andCC = true;
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}
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}
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
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SDValue TargetCC;
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SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
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// Get the condition codes directly from the status register, if its easy.
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// Otherwise a branch will be generated. Note that the AND and BIT
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// instructions generate different flags than CMP, the carry bit can be used
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// for NE/EQ.
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bool Invert = false;
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bool Shift = false;
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bool Convert = true;
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switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
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default:
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Convert = false;
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break;
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case MSP430CC::COND_HS:
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// Res = SRW & 1, no processing is required
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break;
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case MSP430CC::COND_LO:
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// Res = ~(SRW & 1)
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Invert = true;
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break;
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case MSP430CC::COND_NE:
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if (andCC) {
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// C = ~Z, thus Res = SRW & 1, no processing is required
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} else {
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// Res = (SRW >> 1) & 1
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Shift = true;
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}
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break;
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case MSP430CC::COND_E:
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if (andCC) {
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// C = ~Z, thus Res = ~(SRW & 1)
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} else {
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// Res = ~((SRW >> 1) & 1)
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Shift = true;
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}
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Invert = true;
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break;
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}
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EVT VT = Op.getValueType();
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SDValue One = DAG.getConstant(1, VT);
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if (Convert) {
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SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
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MVT::i16, Flag);
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if (Shift)
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// FIXME: somewhere this is turned into a SRL, lower it MSP specific?
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SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
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SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
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if (Invert)
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SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
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return SR;
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} else {
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SDValue Zero = DAG.getConstant(0, VT);
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SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
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SmallVector<SDValue, 4> Ops;
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Ops.push_back(One);
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Ops.push_back(Zero);
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Ops.push_back(TargetCC);
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Ops.push_back(Flag);
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return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
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}
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}
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SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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@ -84,6 +84,7 @@ namespace llvm {
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
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SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG);
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SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG);
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
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116
test/CodeGen/MSP430/setcc.ll
Normal file
116
test/CodeGen/MSP430/setcc.ll
Normal file
@ -0,0 +1,116 @@
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; RUN: llc -march=msp430 < %s | FileCheck %s
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target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:32"
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target triple = "msp430-generic-generic"
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define i16 @sccweqand(i16 %a, i16 %b) nounwind {
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%t1 = and i16 %a, %b
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%t2 = icmp eq i16 %t1, 0
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%t3 = zext i1 %t2 to i16
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ret i16 %t3
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}
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; CHECK: sccweqand:
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; CHECK: bit.w r14, r15
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; CHECK-NEXT: mov.w r2, r15
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; CHECK-NEXT: and.w #1, r15
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; CHECK-NEXT: xor.w #1, r15
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define i16 @sccwneand(i16 %a, i16 %b) nounwind {
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%t1 = and i16 %a, %b
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%t2 = icmp ne i16 %t1, 0
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%t3 = zext i1 %t2 to i16
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ret i16 %t3
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}
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; CHECK: sccwneand:
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; CHECK: bit.w r14, r15
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; CHECK-NEXT: mov.w r2, r15
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; CHECK-NEXT: and.w #1, r15
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define i16 @sccwne(i16 %a, i16 %b) nounwind {
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%t1 = icmp ne i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK:sccwne:
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; CHECK: cmp.w r15, r14
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; CHECK-NEXT: mov.w r2, r15
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; CHECK-NEXT: rra.w r15
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; CHECK-NEXT: and.w #1, r15
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define i16 @sccweq(i16 %a, i16 %b) nounwind {
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%t1 = icmp eq i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK:sccweq:
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; CHECK: cmp.w r15, r14
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; CHECK-NEXT: mov.w r2, r15
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; CHECK-NEXT: rra.w r15
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; CHECK-NEXT: and.w #1, r15
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; CHECK-NEXT: xor.w #1, r15
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define i16 @sccwugt(i16 %a, i16 %b) nounwind {
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%t1 = icmp ugt i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK:sccwugt:
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; CHECK: cmp.w r14, r15
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; CHECK-NEXT: mov.w r2, r15
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; CHECK-NEXT: and.w #1, r15
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; CHECK-NEXT: xor.w #1, r15
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define i16 @sccwuge(i16 %a, i16 %b) nounwind {
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%t1 = icmp uge i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK:sccwuge:
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; CHECK: cmp.w r15, r14
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; CHECK-NEXT: mov.w r2, r15
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; CHECK-NEXT: and.w #1, r15
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define i16 @sccwult(i16 %a, i16 %b) nounwind {
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%t1 = icmp ult i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK:sccwult:
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; CHECK: cmp.w r15, r14
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; CHECK-NEXT: mov.w r2, r15
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; CHECK-NEXT: and.w #1, r15
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; CHECK-NEXT: xor.w #1, r15
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define i16 @sccwule(i16 %a, i16 %b) nounwind {
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%t1 = icmp ule i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK:sccwule:
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; CHECK: cmp.w r14, r15
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; CHECK-NEXT: mov.w r2, r15
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; CHECK-NEXT: and.w #1, r15
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define i16 @sccwsgt(i16 %a, i16 %b) nounwind {
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%t1 = icmp sgt i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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define i16 @sccwsge(i16 %a, i16 %b) nounwind {
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%t1 = icmp sge i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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define i16 @sccwslt(i16 %a, i16 %b) nounwind {
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%t1 = icmp slt i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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define i16 @sccwsle(i16 %a, i16 %b) nounwind {
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%t1 = icmp sle i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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