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https://github.com/c64scene-ar/llvm-6502.git
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Remove unnecessary let hasCtrlDep=1 now it can be inferred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24611 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -193,13 +193,13 @@ let isTerminator = 1 in
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//
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// Return instructions.
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let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep=1 in
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let isTerminator = 1, isReturn = 1, isBarrier = 1 in
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def RET : I<0xC3, RawFrm, (ops), "ret", [(ret)]>;
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let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep=1 in
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let isTerminator = 1, isReturn = 1, isBarrier = 1 in
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def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>;
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// All branches are RawFrm, Void, Branch, and Terminators
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let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in
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let isBranch = 1, isTerminator = 1 in
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class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> :
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I<opcode, RawFrm, ops, asm, pattern>;
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@ -332,30 +332,28 @@ def IN16ri : Ii8<0xE5, RawFrm, (ops i8imm:$port),
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def IN32ri : Ii8<0xE5, RawFrm, (ops i8imm:$port),
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"in{l} {$port, %eax|%EAX, $port}", []>, Imp<[],[EAX]>;
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let hasCtrlDep=1 in {
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def OUT8rr : I<0xEE, RawFrm, (ops),
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"out{b} {%al, %dx|%DX, %AL}",
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[(writeport AL, DX)]>, Imp<[DX, AL], []>;
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def OUT16rr : I<0xEF, RawFrm, (ops),
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"out{w} {%ax, %dx|%DX, %AX}",
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[(writeport AX, DX)]>, Imp<[DX, AX], []>, OpSize;
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def OUT32rr : I<0xEF, RawFrm, (ops),
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"out{l} {%eax, %dx|%DX, %EAX}",
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[(writeport EAX, DX)]>, Imp<[DX, EAX], []>;
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def OUT8rr : I<0xEE, RawFrm, (ops),
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"out{b} {%al, %dx|%DX, %AL}",
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[(writeport AL, DX)]>, Imp<[DX, AL], []>;
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def OUT16rr : I<0xEF, RawFrm, (ops),
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"out{w} {%ax, %dx|%DX, %AX}",
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[(writeport AX, DX)]>, Imp<[DX, AX], []>, OpSize;
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def OUT32rr : I<0xEF, RawFrm, (ops),
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"out{l} {%eax, %dx|%DX, %EAX}",
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[(writeport EAX, DX)]>, Imp<[DX, EAX], []>;
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def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
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"out{b} {%al, $port|$port, %AL}",
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[(writeport AL, (i16 immZExt8:$port))]>,
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Imp<[AL], []>;
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def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
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"out{w} {%ax, $port|$port, %AX}",
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[(writeport AX, (i16 immZExt8:$port))]>,
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Imp<[AX], []>, OpSize;
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def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
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"out{l} {%eax, $port|$port, %EAX}",
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[(writeport EAX, (i16 immZExt8:$port))]>,
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Imp<[EAX], []>;
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}
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def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
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"out{b} {%al, $port|$port, %AL}",
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[(writeport AL, (i16 immZExt8:$port))]>,
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Imp<[AL], []>;
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def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
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"out{w} {%ax, $port|$port, %AX}",
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[(writeport AX, (i16 immZExt8:$port))]>,
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Imp<[AX], []>, OpSize;
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def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
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"out{l} {%eax, $port|$port, %EAX}",
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[(writeport EAX, (i16 immZExt8:$port))]>,
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Imp<[EAX], []>;
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//===----------------------------------------------------------------------===//
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// Move Instructions...
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