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Start using tablegen'd instruction enum list
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7542 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -47,15 +47,8 @@ Pass *createEmitX86CodeToMemory();
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//
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//
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#include "X86GenRegisterNames.inc"
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#include "X86GenRegisterNames.inc"
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/// X86 namespace - This namespace contains all of the register and opcode enums
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// Defines symbolic names for the X86 instructions.
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/// used by the X86 backend.
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//
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///
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#include "X86GenInstrNames.inc"
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namespace X86 {
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// This defines a large number of symbolic names for X86 instruction opcodes.
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enum Opcode {
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#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES) ENUM,
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#include "X86InstrInfo.def"
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};
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}
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#endif
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#endif
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