mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
R600: Cleanup some tests and add missing testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223151 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
301256d436
commit
8d7b46d0d6
@ -1,29 +1,30 @@
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck %s --check-prefix=SI --check-prefix=FUNC
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=EG -check-prefix=FUNC
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
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; FUNC-LABEL: {{^}}fp_to_uint_i32:
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; FUNC-LABEL: {{^}}fp_to_uint_f32_to_i32:
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; SI: v_cvt_u32_f32_e32
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; SI: s_endpgm
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define void @fp_to_uint_i32 (i32 addrspace(1)* %out, float %in) {
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define void @fp_to_uint_f32_to_i32 (i32 addrspace(1)* %out, float %in) {
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%conv = fptoui float %in to i32
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store i32 %conv, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fp_to_uint_v2i32:
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; FUNC-LABEL: {{^}}fp_to_uint_v2f32_to_v2i32:
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: v_cvt_u32_f32_e32
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; SI: v_cvt_u32_f32_e32
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define void @fp_to_uint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
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; SI: v_cvt_u32_f32_e32
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; SI: v_cvt_u32_f32_e32
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define void @fp_to_uint_v2f32_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
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%result = fptoui <2 x float> %in to <2 x i32>
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fp_to_uint_v4i32:
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; FUNC-LABEL: {{^}}fp_to_uint_v4f32_to_v4i32:
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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@ -33,14 +34,14 @@ define void @fp_to_uint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
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; SI: v_cvt_u32_f32_e32
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; SI: v_cvt_u32_f32_e32
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define void @fp_to_uint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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define void @fp_to_uint_v4f32_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%value = load <4 x float> addrspace(1) * %in
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%result = fptoui <4 x float> %value to <4 x i32>
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC: {{^}}fp_to_uint_i64:
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; FUNC: {{^}}fp_to_uint_f32_to_i64:
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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@ -64,13 +65,13 @@ define void @fp_to_uint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspac
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; EG-DAG: CNDE_INT
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; SI: s_endpgm
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define void @fp_to_uint_i64(i64 addrspace(1)* %out, float %x) {
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define void @fp_to_uint_f32_to_i64(i64 addrspace(1)* %out, float %x) {
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%conv = fptoui float %x to i64
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store i64 %conv, i64 addrspace(1)* %out
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ret void
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}
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; FUNC: {{^}}fp_to_uint_v2i64:
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; FUNC: {{^}}fp_to_uint_v2f32_to_v2i64:
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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@ -115,13 +116,13 @@ define void @fp_to_uint_i64(i64 addrspace(1)* %out, float %x) {
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; EG-DAG: CNDE_INT
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; SI: s_endpgm
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define void @fp_to_uint_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) {
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define void @fp_to_uint_v2f32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) {
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%conv = fptoui <2 x float> %x to <2 x i64>
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store <2 x i64> %conv, <2 x i64> addrspace(1)* %out
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ret void
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}
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; FUNC: {{^}}fp_to_uint_v4i64:
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; FUNC: {{^}}fp_to_uint_v4f32_to_v4i64:
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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@ -208,7 +209,7 @@ define void @fp_to_uint_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) {
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; EG-DAG: CNDE_INT
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; SI: s_endpgm
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define void @fp_to_uint_v4i64(<4 x i64> addrspace(1)* %out, <4 x float> %x) {
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define void @fp_to_uint_v4f32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x float> %x) {
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%conv = fptoui <4 x float> %x to <4 x i64>
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store <4 x i64> %conv, <4 x i64> addrspace(1)* %out
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ret void
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@ -1,166 +1,166 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
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;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
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; RUN: llc -march=r600 -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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;EG-CHECK: {{^}}lshr_v2i32:
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;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; FUNC-LABEL: {{^}}lshr_i32:
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; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @lshr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%b_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%a = load i32 addrspace(1)* %in
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%b = load i32 addrspace(1)* %b_ptr
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%result = lshr i32 %a, %b
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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;SI-CHECK: {{^}}lshr_v2i32:
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;SI-CHECK: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; FUNC-LABEL: {{^}}lshr_v2i32:
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; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @lshr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32> addrspace(1) * %in
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%b = load <2 x i32> addrspace(1) * %b_ptr
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%a = load <2 x i32> addrspace(1)* %in
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%b = load <2 x i32> addrspace(1)* %b_ptr
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%result = lshr <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}lshr_v4i32:
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; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;EG-CHECK: {{^}}lshr_v4i32:
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;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI-CHECK: {{^}}lshr_v4i32:
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;SI-CHECK: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32> addrspace(1) * %in
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%b = load <4 x i32> addrspace(1) * %b_ptr
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%a = load <4 x i32> addrspace(1)* %in
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%b = load <4 x i32> addrspace(1)* %b_ptr
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%result = lshr <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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;EG-CHECK: {{^}}lshr_i64:
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;EG-CHECK: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
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;EG-CHECK: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
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;EG-CHECK: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
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;EG_CHECK-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
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;EG-CHECK-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]]
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;EG-CHECK-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}}
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;EG-CHECK-DAG: LSHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}}
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;EG-CHECK-DAG: LSHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}}
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;EG-CHECK-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
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;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
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;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0
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;SI-CHECK: {{^}}lshr_i64:
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;SI-CHECK: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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; FUNC-LABEL: {{^}}lshr_i64:
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; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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; EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
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; EG: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
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; EG: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
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; EG-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
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; EG-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]]
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; EG-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}}
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; EG-DAG: LSHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}}
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; EG-DAG: LSHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}}
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; EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
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; EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
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; EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0
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define void @lshr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
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%b_ptr = getelementptr i64 addrspace(1)* %in, i64 1
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%a = load i64 addrspace(1) * %in
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%b = load i64 addrspace(1) * %b_ptr
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%a = load i64 addrspace(1)* %in
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%b = load i64 addrspace(1)* %b_ptr
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%result = lshr i64 %a, %b
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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;EG-CHECK: {{^}}lshr_v2i64:
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;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
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;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
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;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHA]]
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;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHB]]
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;EG-CHECK-DAG: LSHL {{.*}}, 1
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;EG-CHECK-DAG: LSHL {{.*}}, 1
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;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]]
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;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]]
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;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]]
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;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]]
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;EG-CHECK-DAG: OR_INT
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;EG-CHECK-DAG: OR_INT
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;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-CHECK-DAG: LSHR
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;EG-CHECK-DAG: LSHR
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;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
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;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
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;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0
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;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0
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;EG-CHECK-DAG: CNDE_INT
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;EG-CHECK-DAG: CNDE_INT
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;SI-CHECK: {{^}}lshr_v2i64:
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;SI-CHECK: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;SI-CHECK: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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; FUNC-LABEL: {{^}}lshr_v2i64:
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; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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; EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
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; EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
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; EG-DAG: LSHL {{\*? *}}[[COMPSHA]]
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; EG-DAG: LSHL {{\*? *}}[[COMPSHB]]
|
||||
; EG-DAG: LSHL {{.*}}, 1
|
||||
; EG-DAG: LSHL {{.*}}, 1
|
||||
; EG-DAG: LSHR {{.*}}, [[SHA]]
|
||||
; EG-DAG: LSHR {{.*}}, [[SHB]]
|
||||
; EG-DAG: LSHR {{.*}}, [[SHA]]
|
||||
; EG-DAG: LSHR {{.*}}, [[SHB]]
|
||||
; EG-DAG: OR_INT
|
||||
; EG-DAG: OR_INT
|
||||
; EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
|
||||
; EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
|
||||
; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
|
||||
; EG-DAG: CNDE_INT {{.*}}, 0.0
|
||||
; EG-DAG: CNDE_INT {{.*}}, 0.0
|
||||
; EG-DAG: CNDE_INT
|
||||
; EG-DAG: CNDE_INT
|
||||
define void @lshr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
|
||||
%b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1
|
||||
%a = load <2 x i64> addrspace(1) * %in
|
||||
%b = load <2 x i64> addrspace(1) * %b_ptr
|
||||
%a = load <2 x i64> addrspace(1)* %in
|
||||
%b = load <2 x i64> addrspace(1)* %b_ptr
|
||||
%result = lshr <2 x i64> %a, %b
|
||||
store <2 x i64> %result, <2 x i64> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}lshr_v4i64:
|
||||
; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
|
||||
; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
|
||||
; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
|
||||
; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
|
||||
|
||||
;EG-CHECK: {{^}}lshr_v4i64:
|
||||
;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
|
||||
;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
|
||||
;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]]
|
||||
;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]]
|
||||
;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHA]]
|
||||
;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHB]]
|
||||
;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHC]]
|
||||
;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHD]]
|
||||
;EG-CHECK-DAG: LSHL {{.*}}, 1
|
||||
;EG-CHECK-DAG: LSHL {{.*}}, 1
|
||||
;EG-CHECK-DAG: LSHL {{.*}}, 1
|
||||
;EG-CHECK-DAG: LSHL {{.*}}, 1
|
||||
;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]]
|
||||
;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]]
|
||||
;EG-CHECK-DAG: LSHR {{.*}}, [[SHC]]
|
||||
;EG-CHECK-DAG: LSHR {{.*}}, [[SHD]]
|
||||
;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]]
|
||||
;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]]
|
||||
;EG-CHECK-DAG: LSHR {{.*}}, [[SHC]]
|
||||
;EG-CHECK-DAG: LSHR {{.*}}, [[SHD]]
|
||||
;EG-CHECK-DAG: OR_INT
|
||||
;EG-CHECK-DAG: OR_INT
|
||||
;EG-CHECK-DAG: OR_INT
|
||||
;EG-CHECK-DAG: OR_INT
|
||||
;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
|
||||
;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
|
||||
;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal
|
||||
;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal
|
||||
;EG-CHECK-DAG: LSHR
|
||||
;EG-CHECK-DAG: LSHR
|
||||
;EG-CHECK-DAG: LSHR
|
||||
;EG-CHECK-DAG: LSHR
|
||||
;EG-CHECK-DAG: LSHR
|
||||
;EG-CHECK-DAG: LSHR
|
||||
;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
|
||||
;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
|
||||
;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal
|
||||
;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal
|
||||
;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0
|
||||
;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0
|
||||
;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0
|
||||
;EG-CHECK-DAG: CNDE_INT {{.*}}, 0.0
|
||||
;EG-CHECK-DAG: CNDE_INT
|
||||
;EG-CHECK-DAG: CNDE_INT
|
||||
;EG-CHECK-DAG: CNDE_INT
|
||||
;EG-CHECK-DAG: CNDE_INT
|
||||
|
||||
;SI-CHECK: {{^}}lshr_v4i64:
|
||||
;SI-CHECK: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
|
||||
;SI-CHECK: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
|
||||
;SI-CHECK: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
|
||||
;SI-CHECK: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
|
||||
|
||||
; EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
|
||||
; EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
|
||||
; EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]]
|
||||
; EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]]
|
||||
; EG-DAG: LSHL {{\*? *}}[[COMPSHA]]
|
||||
; EG-DAG: LSHL {{\*? *}}[[COMPSHB]]
|
||||
; EG-DAG: LSHL {{\*? *}}[[COMPSHC]]
|
||||
; EG-DAG: LSHL {{\*? *}}[[COMPSHD]]
|
||||
; EG-DAG: LSHL {{.*}}, 1
|
||||
; EG-DAG: LSHL {{.*}}, 1
|
||||
; EG-DAG: LSHL {{.*}}, 1
|
||||
; EG-DAG: LSHL {{.*}}, 1
|
||||
; EG-DAG: LSHR {{.*}}, [[SHA]]
|
||||
; EG-DAG: LSHR {{.*}}, [[SHB]]
|
||||
; EG-DAG: LSHR {{.*}}, [[SHC]]
|
||||
; EG-DAG: LSHR {{.*}}, [[SHD]]
|
||||
; EG-DAG: LSHR {{.*}}, [[SHA]]
|
||||
; EG-DAG: LSHR {{.*}}, [[SHB]]
|
||||
; EG-DAG: LSHR {{.*}}, [[SHC]]
|
||||
; EG-DAG: LSHR {{.*}}, [[SHD]]
|
||||
; EG-DAG: OR_INT
|
||||
; EG-DAG: OR_INT
|
||||
; EG-DAG: OR_INT
|
||||
; EG-DAG: OR_INT
|
||||
; EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
|
||||
; EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
|
||||
; EG-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal
|
||||
; EG-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: LSHR
|
||||
; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
|
||||
; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
|
||||
; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal
|
||||
; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal
|
||||
; EG-DAG: CNDE_INT {{.*}}, 0.0
|
||||
; EG-DAG: CNDE_INT {{.*}}, 0.0
|
||||
; EG-DAG: CNDE_INT {{.*}}, 0.0
|
||||
; EG-DAG: CNDE_INT {{.*}}, 0.0
|
||||
; EG-DAG: CNDE_INT
|
||||
; EG-DAG: CNDE_INT
|
||||
; EG-DAG: CNDE_INT
|
||||
; EG-DAG: CNDE_INT
|
||||
define void @lshr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
|
||||
%b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1
|
||||
%a = load <4 x i64> addrspace(1) * %in
|
||||
%b = load <4 x i64> addrspace(1) * %b_ptr
|
||||
%a = load <4 x i64> addrspace(1)* %in
|
||||
%b = load <4 x i64> addrspace(1)* %b_ptr
|
||||
%result = lshr <4 x i64> %a, %b
|
||||
store <4 x i64> %result, <4 x i64> addrspace(1)* %out
|
||||
ret void
|
||||
|
||||
@ -1,16 +1,31 @@
|
||||
;RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
|
||||
;RUN: llc -march=r600 -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
|
||||
; RUN: llc -march=r600 -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
|
||||
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
|
||||
|
||||
|
||||
declare i32 @llvm.r600.read.tidig.x() readnone
|
||||
|
||||
;FUNC-LABEL: {{^}}test2:
|
||||
;EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; FUNC-LABEL: {{^}}test_sub_i32:
|
||||
; EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
|
||||
;SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
|
||||
;SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
|
||||
; SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
|
||||
define void @test_sub_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
|
||||
%b_ptr = getelementptr i32 addrspace(1)* %in, i32 1
|
||||
%a = load i32 addrspace(1)* %in
|
||||
%b = load i32 addrspace(1)* %b_ptr
|
||||
%result = sub i32 %a, %b
|
||||
store i32 %result, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
|
||||
|
||||
; FUNC-LABEL: {{^}}test_sub_v2i32:
|
||||
; EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
|
||||
; SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
|
||||
; SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
|
||||
|
||||
define void @test_sub_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
|
||||
%b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
|
||||
%a = load <2 x i32> addrspace(1) * %in
|
||||
%b = load <2 x i32> addrspace(1) * %b_ptr
|
||||
@ -19,18 +34,18 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
|
||||
ret void
|
||||
}
|
||||
|
||||
;FUNC-LABEL: {{^}}test4:
|
||||
;EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
;EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; FUNC-LABEL: {{^}}test_sub_v4i32:
|
||||
; EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
|
||||
;SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
|
||||
;SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
|
||||
;SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
|
||||
;SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
|
||||
; SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
|
||||
; SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
|
||||
; SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
|
||||
; SI: v_sub_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
|
||||
|
||||
define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
|
||||
define void @test_sub_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
|
||||
%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
|
||||
%a = load <4 x i32> addrspace(1) * %in
|
||||
%b = load <4 x i32> addrspace(1) * %b_ptr
|
||||
@ -73,3 +88,39 @@ define void @v_sub_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias
|
||||
store i64 %result, i64 addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}v_test_sub_v2i64:
|
||||
; SI: v_sub_i32_e32
|
||||
; SI: v_subb_u32_e32
|
||||
; SI: v_sub_i32_e32
|
||||
; SI: v_subb_u32_e32
|
||||
define void @v_test_sub_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* noalias %inA, <2 x i64> addrspace(1)* noalias %inB) {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() readnone
|
||||
%a_ptr = getelementptr <2 x i64> addrspace(1)* %inA, i32 %tid
|
||||
%b_ptr = getelementptr <2 x i64> addrspace(1)* %inB, i32 %tid
|
||||
%a = load <2 x i64> addrspace(1)* %a_ptr
|
||||
%b = load <2 x i64> addrspace(1)* %b_ptr
|
||||
%result = sub <2 x i64> %a, %b
|
||||
store <2 x i64> %result, <2 x i64> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}v_test_sub_v4i64:
|
||||
; SI: v_sub_i32_e32
|
||||
; SI: v_subb_u32_e32
|
||||
; SI: v_sub_i32_e32
|
||||
; SI: v_subb_u32_e32
|
||||
; SI: v_sub_i32_e32
|
||||
; SI: v_subb_u32_e32
|
||||
; SI: v_sub_i32_e32
|
||||
; SI: v_subb_u32_e32
|
||||
define void @v_test_sub_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* noalias %inA, <4 x i64> addrspace(1)* noalias %inB) {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() readnone
|
||||
%a_ptr = getelementptr <4 x i64> addrspace(1)* %inA, i32 %tid
|
||||
%b_ptr = getelementptr <4 x i64> addrspace(1)* %inB, i32 %tid
|
||||
%a = load <4 x i64> addrspace(1)* %a_ptr
|
||||
%b = load <4 x i64> addrspace(1)* %b_ptr
|
||||
%result = sub <4 x i64> %a, %b
|
||||
store <4 x i64> %result, <4 x i64> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -2,41 +2,6 @@
|
||||
|
||||
declare i32 @llvm.r600.read.tidig.x() nounwind readnone
|
||||
|
||||
; SI-LABEL: {{^}}uint_to_fp_f64_i32
|
||||
; SI: v_cvt_f64_u32_e32
|
||||
; SI: s_endpgm
|
||||
define void @uint_to_fp_f64_i32(double addrspace(1)* %out, i32 %in) {
|
||||
%cast = uitofp i32 %in to double
|
||||
store double %cast, double addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: {{^}}uint_to_fp_i1_f64:
|
||||
; SI: v_cmp_eq_i32_e64 [[CMP:s\[[0-9]+:[0-9]\]]],
|
||||
; FIXME: We should the VGPR sources for V_CNDMASK are copied from SGPRs,
|
||||
; we should be able to fold the SGPRs into the V_CNDMASK instructions.
|
||||
; SI: v_cndmask_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]]
|
||||
; SI: v_cndmask_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]]
|
||||
; SI: buffer_store_dwordx2
|
||||
; SI: s_endpgm
|
||||
define void @uint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) {
|
||||
%cmp = icmp eq i32 %in, 0
|
||||
%fp = uitofp i1 %cmp to double
|
||||
store double %fp, double addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: {{^}}uint_to_fp_i1_f64_load:
|
||||
; SI: v_cndmask_b32_e64 [[IRESULT:v[0-9]]], 0, 1
|
||||
; SI-NEXT: v_cvt_f64_u32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]]
|
||||
; SI: buffer_store_dwordx2 [[RESULT]]
|
||||
; SI: s_endpgm
|
||||
define void @uint_to_fp_i1_f64_load(double addrspace(1)* %out, i1 %in) {
|
||||
%fp = uitofp i1 %in to double
|
||||
store double %fp, double addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: {{^}}v_uint_to_fp_i64_to_f64
|
||||
; SI: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
|
||||
; SI-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]]
|
||||
@ -53,23 +18,80 @@ define void @v_uint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: {{^}}s_uint_to_fp_f64_i64
|
||||
define void @s_uint_to_fp_f64_i64(double addrspace(1)* %out, i64 %in) {
|
||||
; SI-LABEL: {{^}}s_uint_to_fp_i64_to_f64
|
||||
define void @s_uint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 %in) {
|
||||
%cast = uitofp i64 %in to double
|
||||
store double %cast, double addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: {{^}}s_uint_to_fp_v2f64_v2i64
|
||||
define void @s_uint_to_fp_v2f64_v2i64(<2 x double> addrspace(1)* %out, <2 x i64> %in) {
|
||||
; SI-LABEL: {{^}}s_uint_to_fp_v2i64_to_v2f64
|
||||
define void @s_uint_to_fp_v2i64_to_v2f64(<2 x double> addrspace(1)* %out, <2 x i64> %in) {
|
||||
%cast = uitofp <2 x i64> %in to <2 x double>
|
||||
store <2 x double> %cast, <2 x double> addrspace(1)* %out, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: {{^}}s_uint_to_fp_v4f64_v4i64
|
||||
define void @s_uint_to_fp_v4f64_v4i64(<4 x double> addrspace(1)* %out, <4 x i64> %in) {
|
||||
; SI-LABEL: {{^}}s_uint_to_fp_v4i64_to_v4f64
|
||||
define void @s_uint_to_fp_v4i64_to_v4f64(<4 x double> addrspace(1)* %out, <4 x i64> %in) {
|
||||
%cast = uitofp <4 x i64> %in to <4 x double>
|
||||
store <4 x double> %cast, <4 x double> addrspace(1)* %out, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: {{^}}s_uint_to_fp_i32_to_f64
|
||||
; SI: v_cvt_f64_u32_e32
|
||||
; SI: s_endpgm
|
||||
define void @s_uint_to_fp_i32_to_f64(double addrspace(1)* %out, i32 %in) {
|
||||
%cast = uitofp i32 %in to double
|
||||
store double %cast, double addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: {{^}}s_uint_to_fp_v2i32_to_v2f64
|
||||
; SI: v_cvt_f64_u32_e32
|
||||
; SI: v_cvt_f64_u32_e32
|
||||
; SI: s_endpgm
|
||||
define void @s_uint_to_fp_v2i32_to_v2f64(<2 x double> addrspace(1)* %out, <2 x i32> %in) {
|
||||
%cast = uitofp <2 x i32> %in to <2 x double>
|
||||
store <2 x double> %cast, <2 x double> addrspace(1)* %out, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: {{^}}s_uint_to_fp_v4i32_to_v4f64
|
||||
; SI: v_cvt_f64_u32_e32
|
||||
; SI: v_cvt_f64_u32_e32
|
||||
; SI: v_cvt_f64_u32_e32
|
||||
; SI: v_cvt_f64_u32_e32
|
||||
; SI: s_endpgm
|
||||
define void @s_uint_to_fp_v4i32_to_v4f64(<4 x double> addrspace(1)* %out, <4 x i32> %in) {
|
||||
%cast = uitofp <4 x i32> %in to <4 x double>
|
||||
store <4 x double> %cast, <4 x double> addrspace(1)* %out, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: {{^}}uint_to_fp_i1_to_f64:
|
||||
; SI: v_cmp_eq_i32_e64 [[CMP:s\[[0-9]+:[0-9]\]]],
|
||||
; FIXME: We should the VGPR sources for V_CNDMASK are copied from SGPRs,
|
||||
; we should be able to fold the SGPRs into the V_CNDMASK instructions.
|
||||
; SI: v_cndmask_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]]
|
||||
; SI: v_cndmask_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]]
|
||||
; SI: buffer_store_dwordx2
|
||||
; SI: s_endpgm
|
||||
define void @uint_to_fp_i1_to_f64(double addrspace(1)* %out, i32 %in) {
|
||||
%cmp = icmp eq i32 %in, 0
|
||||
%fp = uitofp i1 %cmp to double
|
||||
store double %fp, double addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: {{^}}uint_to_fp_i1_to_f64_load:
|
||||
; SI: v_cndmask_b32_e64 [[IRESULT:v[0-9]]], 0, 1
|
||||
; SI-NEXT: v_cvt_f64_u32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]]
|
||||
; SI: buffer_store_dwordx2 [[RESULT]]
|
||||
; SI: s_endpgm
|
||||
define void @uint_to_fp_i1_to_f64_load(double addrspace(1)* %out, i1 %in) {
|
||||
%fp = uitofp i1 %in to double
|
||||
store double %fp, double addrspace(1)* %out, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -1,20 +1,31 @@
|
||||
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
|
||||
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
|
||||
|
||||
; FUNC-LABEL: {{^}}uint_to_fp_v2i32:
|
||||
; FUNC-LABEL: {{^}}uint_to_fp_i32_to_f32:
|
||||
; R600-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].Z
|
||||
|
||||
; SI: v_cvt_f32_u32_e32
|
||||
; SI: s_endpgm
|
||||
define void @uint_to_fp_i32_to_f32(float addrspace(1)* %out, i32 %in) {
|
||||
%result = uitofp i32 %in to float
|
||||
store float %result, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}uint_to_fp_v2i32_to_v2f32:
|
||||
; R600-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W
|
||||
; R600-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X
|
||||
|
||||
; SI: v_cvt_f32_u32_e32
|
||||
; SI: v_cvt_f32_u32_e32
|
||||
; SI: s_endpgm
|
||||
define void @uint_to_fp_v2i32(<2 x float> addrspace(1)* %out, <2 x i32> %in) {
|
||||
define void @uint_to_fp_v2i32_to_v2f32(<2 x float> addrspace(1)* %out, <2 x i32> %in) {
|
||||
%result = uitofp <2 x i32> %in to <2 x float>
|
||||
store <2 x float> %result, <2 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}uint_to_fp_v4i32:
|
||||
; FUNC-LABEL: {{^}}uint_to_fp_v4i32_to_v4f32:
|
||||
; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
||||
@ -25,14 +36,14 @@ define void @uint_to_fp_v2i32(<2 x float> addrspace(1)* %out, <2 x i32> %in) {
|
||||
; SI: v_cvt_f32_u32_e32
|
||||
; SI: v_cvt_f32_u32_e32
|
||||
; SI: s_endpgm
|
||||
define void @uint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
|
||||
define void @uint_to_fp_v4i32_to_v4f32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
|
||||
%value = load <4 x i32> addrspace(1) * %in
|
||||
%result = uitofp <4 x i32> %value to <4 x float>
|
||||
store <4 x float> %result, <4 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}uint_to_fp_i64_f32:
|
||||
; FUNC-LABEL: {{^}}uint_to_fp_i64_to_f32:
|
||||
; R600: UINT_TO_FLT
|
||||
; R600: UINT_TO_FLT
|
||||
; R600: MULADD_IEEE
|
||||
@ -40,30 +51,30 @@ define void @uint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspac
|
||||
; SI: v_cvt_f32_u32_e32
|
||||
; SI: v_mad_f32
|
||||
; SI: s_endpgm
|
||||
define void @uint_to_fp_i64_f32(float addrspace(1)* %out, i64 %in) {
|
||||
define void @uint_to_fp_i64_to_f32(float addrspace(1)* %out, i64 %in) {
|
||||
entry:
|
||||
%0 = uitofp i64 %in to float
|
||||
store float %0, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}uint_to_fp_i1_f32:
|
||||
; FUNC-LABEL: {{^}}uint_to_fp_i1_to_f32:
|
||||
; SI: v_cmp_eq_i32_e64 [[CMP:s\[[0-9]+:[0-9]\]]],
|
||||
; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]]
|
||||
; SI: buffer_store_dword [[RESULT]],
|
||||
; SI: s_endpgm
|
||||
define void @uint_to_fp_i1_f32(float addrspace(1)* %out, i32 %in) {
|
||||
define void @uint_to_fp_i1_to_f32(float addrspace(1)* %out, i32 %in) {
|
||||
%cmp = icmp eq i32 %in, 0
|
||||
%fp = uitofp i1 %cmp to float
|
||||
store float %fp, float addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}uint_to_fp_i1_f32_load:
|
||||
; FUNC-LABEL: {{^}}uint_to_fp_i1_to_f32_load:
|
||||
; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0
|
||||
; SI: buffer_store_dword [[RESULT]],
|
||||
; SI: s_endpgm
|
||||
define void @uint_to_fp_i1_f32_load(float addrspace(1)* %out, i1 %in) {
|
||||
define void @uint_to_fp_i1_to_f32_load(float addrspace(1)* %out, i1 %in) {
|
||||
%fp = uitofp i1 %in to float
|
||||
store float %fp, float addrspace(1)* %out, align 4
|
||||
ret void
|
||||
|
||||
@ -1,34 +1,78 @@
|
||||
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
|
||||
;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
|
||||
; RUN: llc -march=r600 -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
|
||||
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
|
||||
|
||||
;The code generated by urem is long and complex and may frequently change.
|
||||
;The goal of this test is to make sure the ISel doesn't fail when it gets
|
||||
;a v2i32/v4i32 urem
|
||||
; The code generated by urem is long and complex and may frequently
|
||||
; change. The goal of this test is to make sure the ISel doesn't fail
|
||||
; when it gets a v2i32/v4i32 urem
|
||||
|
||||
;EG-CHECK: {{^}}test2:
|
||||
;EG-CHECK: CF_END
|
||||
;SI-CHECK: {{^}}test2:
|
||||
;SI-CHECK: s_endpgm
|
||||
; FUNC-LABEL: {{^}}test_urem_i32:
|
||||
; SI: s_endpgm
|
||||
; EG: CF_END
|
||||
define void @test_urem_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
|
||||
%b_ptr = getelementptr i32 addrspace(1)* %in, i32 1
|
||||
%a = load i32 addrspace(1)* %in
|
||||
%b = load i32 addrspace(1)* %b_ptr
|
||||
%result = urem i32 %a, %b
|
||||
store i32 %result, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
|
||||
; FUNC-LABEL: {{^}}test_urem_v2i32:
|
||||
; SI: s_endpgm
|
||||
; EG: CF_END
|
||||
define void @test_urem_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
|
||||
%b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
|
||||
%a = load <2 x i32> addrspace(1) * %in
|
||||
%b = load <2 x i32> addrspace(1) * %b_ptr
|
||||
%a = load <2 x i32> addrspace(1)* %in
|
||||
%b = load <2 x i32> addrspace(1)* %b_ptr
|
||||
%result = urem <2 x i32> %a, %b
|
||||
store <2 x i32> %result, <2 x i32> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
;EG-CHECK: {{^}}test4:
|
||||
;EG-CHECK: CF_END
|
||||
;SI-CHECK: {{^}}test4:
|
||||
;SI-CHECK: s_endpgm
|
||||
|
||||
define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
|
||||
; FUNC-LABEL: {{^}}test_urem_v4i32:
|
||||
; SI: s_endpgm
|
||||
; EG: CF_END
|
||||
define void @test_urem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
|
||||
%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
|
||||
%a = load <4 x i32> addrspace(1) * %in
|
||||
%b = load <4 x i32> addrspace(1) * %b_ptr
|
||||
%a = load <4 x i32> addrspace(1)* %in
|
||||
%b = load <4 x i32> addrspace(1)* %b_ptr
|
||||
%result = urem <4 x i32> %a, %b
|
||||
store <4 x i32> %result, <4 x i32> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}test_urem_i64:
|
||||
; SI: s_endpgm
|
||||
; EG: CF_END
|
||||
define void @test_urem_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
|
||||
%b_ptr = getelementptr i64 addrspace(1)* %in, i64 1
|
||||
%a = load i64 addrspace(1)* %in
|
||||
%b = load i64 addrspace(1)* %b_ptr
|
||||
%result = urem i64 %a, %b
|
||||
store i64 %result, i64 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}test_urem_v2i64:
|
||||
; SI: s_endpgm
|
||||
; EG: CF_END
|
||||
define void @test_urem_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
|
||||
%b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1
|
||||
%a = load <2 x i64> addrspace(1)* %in
|
||||
%b = load <2 x i64> addrspace(1)* %b_ptr
|
||||
%result = urem <2 x i64> %a, %b
|
||||
store <2 x i64> %result, <2 x i64> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}test_urem_v4i64:
|
||||
; SI: s_endpgm
|
||||
; EG: CF_END
|
||||
define void @test_urem_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
|
||||
%b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1
|
||||
%a = load <4 x i64> addrspace(1)* %in
|
||||
%b = load <4 x i64> addrspace(1)* %b_ptr
|
||||
%result = urem <4 x i64> %a, %b
|
||||
store <4 x i64> %result, <4 x i64> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user