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Add instruction encodings / disassembly support for u6 / lu6 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173086 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne
parent
9b709f8b3f
commit
8da5434346
@ -107,12 +107,22 @@ class _FLRU6<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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let Inst{9-0} = b{15-6};
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}
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class _FU6<dag outs, dag ins, string asmstr, list<dag> pattern>
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class _FU6<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<2, outs, ins, asmstr, pattern> {
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bits<6> a;
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let Inst{15-6} = opc;
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let Inst{5-0} = a;
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}
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class _FLU6<dag outs, dag ins, string asmstr, list<dag> pattern>
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class _FLU6<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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bits<16> a;
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let Inst{31-22} = opc;
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let Inst{21-16} = a{5-0};
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let Inst{15-10} = 0b111100;
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let Inst{9-0} = a{15-6};
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}
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class _FU10<dag outs, dag ins, string asmstr, list<dag> pattern>
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@ -288,36 +288,23 @@ multiclass FRU6_LRU6_cp<bits<6> opc, string OpcStr> {
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}
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// U6
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multiclass FU6_LU6<string OpcStr, SDNode OpNode> {
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def _u6: _FU6<
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(outs), (ins i32imm:$b),
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!strconcat(OpcStr, " $b"),
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[(OpNode immU6:$b)]>;
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def _lu6: _FLU6<
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(outs), (ins i32imm:$b),
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!strconcat(OpcStr, " $b"),
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[(OpNode immU16:$b)]>;
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}
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multiclass FU6_LU6_int<string OpcStr, Intrinsic Int> {
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def _u6: _FU6<
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(outs), (ins i32imm:$b),
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!strconcat(OpcStr, " $b"),
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[(Int immU6:$b)]>;
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def _lu6: _FLU6<
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(outs), (ins i32imm:$b),
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!strconcat(OpcStr, " $b"),
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[(Int immU16:$b)]>;
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multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> {
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def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
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[(OpNode immU6:$a)]>;
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def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
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[(OpNode immU16:$a)]>;
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}
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multiclass FU6_LU6_np<string OpcStr> {
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def _u6: _FU6<
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(outs), (ins i32imm:$b),
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!strconcat(OpcStr, " $b"),
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[]>;
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def _lu6: _FLU6<
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(outs), (ins i32imm:$b),
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!strconcat(OpcStr, " $b"),
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[]>;
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multiclass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> {
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def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
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[(Int immU6:$a)]>;
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def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
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[(Int immU16:$a)]>;
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}
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multiclass FU6_LU6_np<bits<10> opc, string OpcStr> {
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def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
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def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
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}
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// U10
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@ -628,60 +615,46 @@ defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">;
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// U6
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let Defs = [SP], Uses = [SP] in {
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let neverHasSideEffects = 1 in
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defm EXTSP : FU6_LU6_np<"extsp">;
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defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">;
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let mayStore = 1 in
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defm ENTSP : FU6_LU6_np<"entsp">;
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defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">;
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let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in {
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defm RETSP : FU6_LU6<"retsp", XCoreRetsp>;
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defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>;
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}
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}
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// TODO extdp, kentsp, krestsp, blat
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// getsr, kalli
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let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
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def BRBU_u6 : _FU6<
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(outs),
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(ins brtarget:$target),
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"bu $target",
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[]>;
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def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>;
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def BRBU_lu6 : _FLU6<
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(outs),
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(ins brtarget:$target),
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"bu $target",
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[]>;
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def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>;
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def BRFU_u6 : _FU6<
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(outs),
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(ins brtarget:$target),
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"bu $target",
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[]>;
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def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
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def BRFU_lu6 : _FLU6<
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(outs),
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(ins brtarget:$target),
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"bu $target",
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[]>;
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def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
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}
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//let Uses = [CP] in ...
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let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
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def LDAWCP_u6: _FU6<(outs), (ins MEMii:$a), "ldaw r11, cp[$a]", []>;
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def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]",
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[]>;
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let Defs = [R11], isReMaterializable = 1 in
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def LDAWCP_lu6: _FLU6<(outs), (ins MEMii:$a), "ldaw r11, cp[$a]",
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def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]",
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[(set R11, ADDRcpii:$a)]>;
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defm SETSR : FU6_LU6_int<"setsr", int_xcore_setsr>;
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defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>;
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defm CLRSR : FU6_LU6_int<"clrsr", int_xcore_clrsr>;
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defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>;
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// setsr may cause a branch if it is used to enable events. clrsr may
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// branch if it is executed while events are enabled.
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let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in {
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defm SETSR_branch : FU6_LU6_np<"setsr">;
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defm CLRSR_branch : FU6_LU6_np<"clrsr">;
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let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
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isCodeGenOnly = 1 in {
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defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">;
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defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">;
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}
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// U10
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@ -392,3 +392,53 @@
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# CHECK: stw r0, sp[8761]
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0x88 0xf0 0x39 0x54
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# u6 / lu6 instructions
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# CHECK: bu -20
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0x14 0x77
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# CHECK: bu -1000
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0x0f 0xf0 0x28 0x77
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# CHECK: bu 24
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0x18 0x73
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# CHECK: bu 2231
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0x22 0xf0 0x37 0x73
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# CHECK: extsp 9
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0x89 0x77
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# CHECK: extsp 5721
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0x59 0xf0 0x99 0x77
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# CHECK: clrsr 60
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0x3c 0x7b
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# CHECK: clrsr 64391
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0xee 0xf3 0x07 0x7b
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# CHECK: entsp 1
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0x41 0x77
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# CHECK: entsp 70
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0x01 0xf0 0x46 0x77
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# CHECK: ldaw r11, cp[5]
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0x45 0x7f
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# CHECK: ldaw r11, cp[33000]
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0x03 0xf2 0x68 0x7f
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# CHECK: retsp 40
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0xe8 0x77
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# CHECK: retsp 52010
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0x2c 0xf3 0xea 0x77
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# CHECK: setsr 42
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0x6a 0x7b
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# CHECK: setsr 21863
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0x55 0xf1 0x67 0x7b
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