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Add (untested) support for MULHS and MULHU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21107 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1818,6 +1818,57 @@ unsigned ISel::SelectExpr(SDOperand N) {
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BuildMI(BB, X86::FCHS, 1, Result).addReg(Tmp1);
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return Result;
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case ISD::MULHU:
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switch (N.getValueType()) {
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default: assert(0 && "Unsupported VT!");
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case MVT::i8: Tmp2 = X86::MUL8r; break;
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case MVT::i16: Tmp2 = X86::MUL16r; break;
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case MVT::i32: Tmp2 = X86::MUL32r; break;
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}
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// FALL THROUGH
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case ISD::MULHS: {
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unsigned MovOpc, LowReg, HiReg;
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switch (N.getValueType()) {
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default: assert(0 && "Unsupported VT!");
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case MVT::i8:
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MovOpc = X86::MOV8rr;
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LowReg = X86::AL;
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HiReg = X86::AH;
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Opc = X86::IMUL8r;
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break;
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case MVT::i16:
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MovOpc = X86::MOV16rr;
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LowReg = X86::AX;
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HiReg = X86::DX;
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Opc = X86::IMUL16r;
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break;
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case MVT::i32:
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MovOpc = X86::MOV32rr;
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LowReg = X86::EAX;
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HiReg = X86::EDX;
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Opc = X86::IMUL32r;
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break;
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}
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if (Node->getOpcode() != ISD::MULHS)
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Opc = Tmp2; // Get the MULHU opcode.
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Op0 = Node->getOperand(0);
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Op1 = Node->getOperand(1);
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if (getRegPressure(Op0) > getRegPressure(Op1)) {
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Tmp1 = SelectExpr(Op0);
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Tmp2 = SelectExpr(Op1);
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} else {
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Tmp2 = SelectExpr(Op1);
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Tmp1 = SelectExpr(Op0);
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}
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// FIXME: Implement folding of loads into the memory operands here!
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BuildMI(BB, MovOpc, 1, LowReg).addReg(Tmp1);
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BuildMI(BB, Opc, 1).addReg(Tmp2);
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BuildMI(BB, MovOpc, 1, Result).addReg(HiReg);
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return Result;
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}
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case ISD::SUB:
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case ISD::MUL:
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case ISD::AND:
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