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https://github.com/c64scene-ar/llvm-6502.git
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AArch64: fix vector-immediate BIC/ORR on big-endian devices.
Follow up to r217138, extending the logic to other NEON-immediate instructions. As before, the instruction already performs the correct operation and we're just using a different type for convenience, so we want a true nop-cast. Patch by Asiri Rathnayake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217159 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
d3a511ec07
commit
8dcac5d77a
@ -5148,7 +5148,7 @@ SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
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SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, MVT::i32),
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DAG.getConstant(0, MVT::i32));
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return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
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@ -5157,7 +5157,7 @@ SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
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SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, MVT::i32),
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DAG.getConstant(8, MVT::i32));
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return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
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@ -5166,7 +5166,7 @@ SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
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SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, MVT::i32),
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DAG.getConstant(16, MVT::i32));
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return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
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@ -5175,7 +5175,7 @@ SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
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SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, MVT::i32),
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DAG.getConstant(24, MVT::i32));
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return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
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@ -5184,7 +5184,7 @@ SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
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SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, MVT::i32),
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DAG.getConstant(0, MVT::i32));
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return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
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@ -5193,7 +5193,7 @@ SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
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SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, MVT::i32),
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DAG.getConstant(8, MVT::i32));
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return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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}
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@ -5348,7 +5348,7 @@ SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
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SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, MVT::i32),
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DAG.getConstant(0, MVT::i32));
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return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
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@ -5357,7 +5357,7 @@ SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
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SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, MVT::i32),
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DAG.getConstant(8, MVT::i32));
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return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
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@ -5366,7 +5366,7 @@ SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
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SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, MVT::i32),
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DAG.getConstant(16, MVT::i32));
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return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
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@ -5375,7 +5375,7 @@ SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
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SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, MVT::i32),
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DAG.getConstant(24, MVT::i32));
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return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
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@ -5384,7 +5384,7 @@ SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
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SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, MVT::i32),
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DAG.getConstant(0, MVT::i32));
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return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
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@ -5393,7 +5393,7 @@ SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
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SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
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DAG.getConstant(CnstVal, MVT::i32),
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DAG.getConstant(8, MVT::i32));
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return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
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return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
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}
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}
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@ -4962,36 +4962,47 @@ def : Pat<(trap), (BRK 1)>;
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def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
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def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
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def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>;
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def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
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def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
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def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
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def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>;
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def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
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def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
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def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>;
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def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
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def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
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def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
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def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
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def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
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def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
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def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
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def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
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def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
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def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
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def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
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def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
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def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>;
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// Natural vector casts (128 bit)
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def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
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def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
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def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>;
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def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
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def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
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def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
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def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>;
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def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
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def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
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def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>;
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def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
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def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
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def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
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def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
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def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
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@ -5003,6 +5014,7 @@ def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
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def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
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def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
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def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
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def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>;
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def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
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def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
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@ -242,6 +242,138 @@ define i16 @mvni_modimm_t8() nounwind {
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ret i16 %el
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}
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; CHECK-LABEL: bic_modimm_t1:
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define i16 @bic_modimm_t1() nounwind {
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; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
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; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #0x1
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; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
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%in = load <8 x i16>* @vec_v8i16
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%rv = and <8 x i16> %in, <i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535>
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%el = extractelement <8 x i16> %rv, i32 0
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ret i16 %el
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}
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; CHECK-LABEL: bic_modimm_t2:
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define i16 @bic_modimm_t2() nounwind {
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; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
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; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #0x1, lsl #8
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; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
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%in = load <8 x i16>* @vec_v8i16
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%rv = and <8 x i16> %in, <i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535>
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%el = extractelement <8 x i16> %rv, i32 0
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ret i16 %el
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}
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; CHECK-LABEL: bic_modimm_t3:
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define i16 @bic_modimm_t3() nounwind {
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; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
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; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #0x1, lsl #16
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; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
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%in = load <8 x i16>* @vec_v8i16
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%rv = and <8 x i16> %in, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
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%el = extractelement <8 x i16> %rv, i32 0
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ret i16 %el
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}
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; CHECK-LABEL: bic_modimm_t4:
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define i16 @bic_modimm_t4() nounwind {
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; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
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; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #0x1, lsl #24
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; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
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%in = load <8 x i16>* @vec_v8i16
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%rv = and <8 x i16> %in, <i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279>
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%el = extractelement <8 x i16> %rv, i32 0
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ret i16 %el
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}
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; CHECK-LABEL: bic_modimm_t5:
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define i16 @bic_modimm_t5() nounwind {
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; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
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; CHECK-NEXT: bic v[[REG2:[0-9]+]].8h, #0x1
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; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
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%in = load <8 x i16>* @vec_v8i16
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%rv = and <8 x i16> %in, <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534>
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%el = extractelement <8 x i16> %rv, i32 0
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ret i16 %el
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}
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; CHECK-LABEL: bic_modimm_t6:
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define i16 @bic_modimm_t6() nounwind {
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; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
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; CHECK-NEXT: bic v[[REG2:[0-9]+]].8h, #0x1, lsl #8
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; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
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%in = load <8 x i16>* @vec_v8i16
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%rv = and <8 x i16> %in, <i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279>
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%el = extractelement <8 x i16> %rv, i32 0
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ret i16 %el
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}
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; CHECK-LABEL: orr_modimm_t1:
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define i16 @orr_modimm_t1() nounwind {
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; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
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; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #0x1
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; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
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%in = load <8 x i16>* @vec_v8i16
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%rv = or <8 x i16> %in, <i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0>
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%el = extractelement <8 x i16> %rv, i32 0
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ret i16 %el
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}
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; CHECK-LABEL: orr_modimm_t2:
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define i16 @orr_modimm_t2() nounwind {
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; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
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; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #0x1, lsl #8
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; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
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%in = load <8 x i16>* @vec_v8i16
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%rv = or <8 x i16> %in, <i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0>
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%el = extractelement <8 x i16> %rv, i32 0
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ret i16 %el
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}
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; CHECK-LABEL: orr_modimm_t3:
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define i16 @orr_modimm_t3() nounwind {
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; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
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; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #0x1, lsl #16
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; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
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%in = load <8 x i16>* @vec_v8i16
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%rv = or <8 x i16> %in, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>
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%el = extractelement <8 x i16> %rv, i32 0
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ret i16 %el
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}
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; CHECK-LABEL: orr_modimm_t4:
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define i16 @orr_modimm_t4() nounwind {
|
||||
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
|
||||
; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #0x1, lsl #24
|
||||
; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
|
||||
%in = load <8 x i16>* @vec_v8i16
|
||||
%rv = or <8 x i16> %in, <i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256>
|
||||
%el = extractelement <8 x i16> %rv, i32 0
|
||||
ret i16 %el
|
||||
}
|
||||
|
||||
; CHECK-LABEL: orr_modimm_t5:
|
||||
define i16 @orr_modimm_t5() nounwind {
|
||||
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
|
||||
; CHECK-NEXT: orr v[[REG2:[0-9]+]].8h, #0x1
|
||||
; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
|
||||
%in = load <8 x i16>* @vec_v8i16
|
||||
%rv = or <8 x i16> %in, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
|
||||
%el = extractelement <8 x i16> %rv, i32 0
|
||||
ret i16 %el
|
||||
}
|
||||
|
||||
; CHECK-LABEL: orr_modimm_t6:
|
||||
define i16 @orr_modimm_t6() nounwind {
|
||||
; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
|
||||
; CHECK-NEXT: orr v[[REG2:[0-9]+]].8h, #0x1, lsl #8
|
||||
; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
|
||||
%in = load <8 x i16>* @vec_v8i16
|
||||
%rv = or <8 x i16> %in, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
|
||||
%el = extractelement <8 x i16> %rv, i32 0
|
||||
ret i16 %el
|
||||
}
|
||||
|
||||
declare i8 @f_v8i8(<8 x i8> %arg)
|
||||
declare i16 @f_v4i16(<4 x i16> %arg)
|
||||
declare i32 @f_v2i32(<2 x i32> %arg)
|
||||
@ -249,8 +381,8 @@ declare i8 @f_v16i8(<16 x i8> %arg)
|
||||
declare i16 @f_v8i16(<8 x i16> %arg)
|
||||
declare i32 @f_v4i32(<4 x i32> %arg)
|
||||
|
||||
; CHECK-LABEL: movi_modimm_t1_call:
|
||||
define void @movi_modimm_t1_call() {
|
||||
; CHECK-LABEL: modimm_t1_call:
|
||||
define void @modimm_t1_call() {
|
||||
; CHECK: movi v[[REG1:[0-9]+]].2s, #0x8
|
||||
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
|
||||
; CHECK-NEXT: bl f_v8i8
|
||||
@ -282,8 +414,8 @@ define void @movi_modimm_t1_call() {
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: movi_modimm_t2_call:
|
||||
define void @movi_modimm_t2_call() {
|
||||
; CHECK-LABEL: modimm_t2_call:
|
||||
define void @modimm_t2_call() {
|
||||
; CHECK: movi v[[REG1:[0-9]+]].2s, #0x8, lsl #8
|
||||
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
|
||||
; CHECK-NEXT: bl f_v8i8
|
||||
@ -315,8 +447,8 @@ define void @movi_modimm_t2_call() {
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: movi_modimm_t3_call:
|
||||
define void @movi_modimm_t3_call() {
|
||||
; CHECK-LABEL: modimm_t3_call:
|
||||
define void @modimm_t3_call() {
|
||||
; CHECK: movi v[[REG1:[0-9]+]].2s, #0x8, lsl #16
|
||||
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
|
||||
; CHECK-NEXT: bl f_v8i8
|
||||
@ -348,8 +480,8 @@ define void @movi_modimm_t3_call() {
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: movi_modimm_t4_call:
|
||||
define void @movi_modimm_t4_call() {
|
||||
; CHECK-LABEL: modimm_t4_call:
|
||||
define void @modimm_t4_call() {
|
||||
; CHECK: movi v[[REG1:[0-9]+]].2s, #0x8, lsl #24
|
||||
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
|
||||
; CHECK-NEXT: bl f_v8i8
|
||||
@ -381,8 +513,8 @@ define void @movi_modimm_t4_call() {
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: movi_modimm_t5_call:
|
||||
define void @movi_modimm_t5_call() {
|
||||
; CHECK-LABEL: modimm_t5_call:
|
||||
define void @modimm_t5_call() {
|
||||
; CHECK: movi v[[REG1:[0-9]+]].4h, #0x8
|
||||
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
|
||||
; CHECK-NEXT: bl f_v8i8
|
||||
@ -414,8 +546,8 @@ define void @movi_modimm_t5_call() {
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: movi_modimm_t6_call:
|
||||
define void @movi_modimm_t6_call() {
|
||||
; CHECK-LABEL: modimm_t6_call:
|
||||
define void @modimm_t6_call() {
|
||||
; CHECK: movi v[[REG1:[0-9]+]].4h, #0x8, lsl #8
|
||||
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
|
||||
; CHECK-NEXT: bl f_v8i8
|
||||
@ -447,8 +579,8 @@ define void @movi_modimm_t6_call() {
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: movi_modimm_t7_call:
|
||||
define void @movi_modimm_t7_call() {
|
||||
; CHECK-LABEL: modimm_t7_call:
|
||||
define void @modimm_t7_call() {
|
||||
; CHECK: movi v[[REG1:[0-9]+]].2s, #0x8, msl #8
|
||||
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
|
||||
; CHECK-NEXT: bl f_v8i8
|
||||
@ -480,8 +612,8 @@ define void @movi_modimm_t7_call() {
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: movi_modimm_t8_call:
|
||||
define void @movi_modimm_t8_call() {
|
||||
; CHECK-LABEL: modimm_t8_call:
|
||||
define void @modimm_t8_call() {
|
||||
; CHECK: movi v[[REG1:[0-9]+]].2s, #0x8, msl #16
|
||||
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
|
||||
; CHECK-NEXT: bl f_v8i8
|
||||
@ -513,8 +645,8 @@ define void @movi_modimm_t8_call() {
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: movi_modimm_t9_call:
|
||||
define void @movi_modimm_t9_call() {
|
||||
; CHECK-LABEL: modimm_t9_call:
|
||||
define void @modimm_t9_call() {
|
||||
; CHECK: movi v[[REG1:[0-9]+]].8b, #0x8
|
||||
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
|
||||
; CHECK-NEXT: bl f_v8i8
|
||||
@ -546,8 +678,8 @@ define void @movi_modimm_t9_call() {
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: movi_modimm_t10_call:
|
||||
define void @movi_modimm_t10_call() {
|
||||
; CHECK-LABEL: modimm_t10_call:
|
||||
define void @modimm_t10_call() {
|
||||
; CHECK: movi d[[REG1:[0-9]+]], #0x0000ff000000ff
|
||||
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
|
||||
; CHECK-NEXT: bl f_v8i8
|
||||
@ -579,8 +711,8 @@ define void @movi_modimm_t10_call() {
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: fmov_modimm_t11_call:
|
||||
define void @fmov_modimm_t11_call() {
|
||||
; CHECK-LABEL: modimm_t11_call:
|
||||
define void @modimm_t11_call() {
|
||||
; CHECK: fmov v[[REG1:[0-9]+]].2s, #4.00000000
|
||||
; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
|
||||
; CHECK-NEXT: bl f_v8i8
|
||||
@ -612,8 +744,8 @@ define void @fmov_modimm_t11_call() {
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: fmov_modimm_t12_call:
|
||||
define void @fmov_modimm_t12_call() {
|
||||
; CHECK-LABEL: modimm_t12_call:
|
||||
define void @modimm_t12_call() {
|
||||
; CHECK: fmov v[[REG1:[0-9]+]].2d, #0.18750000
|
||||
; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
|
||||
; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
|
||||
|
||||
Loading…
Reference in New Issue
Block a user