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RegAlloc superpass: includes phi elimination, coalescing, and scheduling.
Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -49,10 +49,7 @@ namespace {
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public:
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static char ID;
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RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1),
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isBulkSpilling(false) {
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initializePHIEliminationPass(*PassRegistry::getPassRegistry());
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initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
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}
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isBulkSpilling(false) {}
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private:
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const TargetMachine *TM;
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MachineFunction *MF;
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@@ -137,8 +134,6 @@ namespace {
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequiredID(PHIEliminationID);
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AU.addRequiredID(TwoAddressInstructionPassID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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@@ -1089,6 +1084,8 @@ bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
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RegClassInfo.runOnMachineFunction(Fn);
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UsedInInstr.resize(TRI->getNumRegs());
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assert(!MRI->isSSA() && "regalloc requires leaving SSA");
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// initialize the virtual->physical register map to have a 'null'
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// mapping for all virtual registers
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StackSlotForVirtReg.resize(MRI->getNumVirtRegs());
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