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[InstCombine][X86][SSE] Replace sign/zero extension intrinsics with native IR
Now that we are generating sane codegen for vector sext/zext nodes on SSE targets, this patch uses instcombine to replace the SSE41/AVX2 pmovsx and pmovzx intrinsics with the equivalent native IR code. Differential Revision: http://reviews.llvm.org/D11503 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243303 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim
parent
2deaa2924e
commit
8e2e335276
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@ -198,6 +198,24 @@ Instruction *InstCombiner::SimplifyMemSet(MemSetInst *MI) {
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return nullptr;
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}
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static Value *SimplifyX86extend(const IntrinsicInst &II,
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InstCombiner::BuilderTy &Builder,
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bool SignExtend) {
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VectorType *SrcTy = cast<VectorType>(II.getArgOperand(0)->getType());
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VectorType *DstTy = cast<VectorType>(II.getType());
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unsigned NumDstElts = DstTy->getNumElements();
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// Extract a subvector of the first NumDstElts lanes and sign/zero extend.
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SmallVector<int, 8> ShuffleMask;
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for (int i = 0; i != NumDstElts; ++i)
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ShuffleMask.push_back(i);
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Value *SV = Builder.CreateShuffleVector(II.getArgOperand(0),
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UndefValue::get(SrcTy), ShuffleMask);
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return SignExtend ? Builder.CreateSExt(SV, DstTy)
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: Builder.CreateZExt(SV, DstTy);
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}
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static Value *SimplifyX86insertps(const IntrinsicInst &II,
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InstCombiner::BuilderTy &Builder) {
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if (auto *CInt = dyn_cast<ConstantInt>(II.getArgOperand(2))) {
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@ -778,25 +796,38 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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Builder->CreateVectorSplat(VWidth, VTCI));
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}
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case Intrinsic::x86_sse41_pmovsxbd:
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case Intrinsic::x86_sse41_pmovsxbq:
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case Intrinsic::x86_sse41_pmovsxbw:
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case Intrinsic::x86_sse41_pmovsxwd:
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case Intrinsic::x86_sse41_pmovsxdq:
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case Intrinsic::x86_sse41_pmovzxbw:
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case Intrinsic::x86_sse41_pmovzxwd:
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case Intrinsic::x86_sse41_pmovzxdq: {
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// pmov{s|z}x ignores the upper half of their input vectors.
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unsigned VWidth =
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cast<VectorType>(II->getArgOperand(0)->getType())->getNumElements();
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unsigned LowHalfElts = VWidth / 2;
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APInt InputDemandedElts(APInt::getBitsSet(VWidth, 0, LowHalfElts));
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APInt UndefElts(VWidth, 0);
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if (Value *TmpV = SimplifyDemandedVectorElts(
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II->getArgOperand(0), InputDemandedElts, UndefElts)) {
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II->setArgOperand(0, TmpV);
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return II;
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}
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case Intrinsic::x86_sse41_pmovsxwd:
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case Intrinsic::x86_sse41_pmovsxwq:
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case Intrinsic::x86_avx2_pmovsxbd:
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case Intrinsic::x86_avx2_pmovsxbq:
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case Intrinsic::x86_avx2_pmovsxbw:
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case Intrinsic::x86_avx2_pmovsxdq:
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case Intrinsic::x86_avx2_pmovsxwd:
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case Intrinsic::x86_avx2_pmovsxwq:
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if (Value *V = SimplifyX86extend(*II, *Builder, true))
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return ReplaceInstUsesWith(*II, V);
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break;
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}
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case Intrinsic::x86_sse41_pmovzxbd:
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case Intrinsic::x86_sse41_pmovzxbq:
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case Intrinsic::x86_sse41_pmovzxbw:
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case Intrinsic::x86_sse41_pmovzxdq:
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case Intrinsic::x86_sse41_pmovzxwd:
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case Intrinsic::x86_sse41_pmovzxwq:
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case Intrinsic::x86_avx2_pmovzxbd:
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case Intrinsic::x86_avx2_pmovzxbq:
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case Intrinsic::x86_avx2_pmovzxbw:
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case Intrinsic::x86_avx2_pmovzxdq:
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case Intrinsic::x86_avx2_pmovzxwd:
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case Intrinsic::x86_avx2_pmovzxwq:
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if (Value *V = SimplifyX86extend(*II, *Builder, false))
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return ReplaceInstUsesWith(*II, V);
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break;
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case Intrinsic::x86_sse41_insertps:
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if (Value *V = SimplifyX86insertps(*II, *Builder))
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return ReplaceInstUsesWith(*II, V);
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@ -138,22 +138,6 @@ declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>)
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declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>)
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declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>)
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; <rdar://problem/6945110>
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define <4 x i32> @kernel3_vertical(<4 x i16> * %src, <8 x i16> * %foo) nounwind {
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entry:
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%tmp = load <4 x i16>, <4 x i16>* %src
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%tmp1 = load <8 x i16>, <8 x i16>* %foo
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; CHECK: %tmp2 = shufflevector
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%tmp2 = shufflevector <4 x i16> %tmp, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
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; pmovzxwd ignores the upper 64-bits of its input; -instcombine should remove this shuffle:
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; CHECK-NOT: shufflevector
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
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; CHECK-NEXT: pmovzxwd
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%0 = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp3)
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ret <4 x i32> %0
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}
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declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone
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define <4 x float> @dead_shuffle_elt(<4 x float> %x, <2 x float> %y) nounwind {
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entry:
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; CHECK-LABEL: define <4 x float> @dead_shuffle_elt(
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136
test/Transforms/InstCombine/x86-pmovsx.ll
Normal file
136
test/Transforms/InstCombine/x86-pmovsx.ll
Normal file
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@ -0,0 +1,136 @@
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; RUN: opt < %s -instcombine -S | FileCheck %s
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declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
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declare <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8>) nounwind readnone
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declare <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16>) nounwind readnone
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declare <8 x i32> @llvm.x86.avx2.pmovsxbd(<16 x i8>) nounwind readnone
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declare <4 x i64> @llvm.x86.avx2.pmovsxbq(<16 x i8>) nounwind readnone
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declare <16 x i16> @llvm.x86.avx2.pmovsxbw(<16 x i8>) nounwind readnone
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declare <4 x i64> @llvm.x86.avx2.pmovsxdq(<4 x i32>) nounwind readnone
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declare <8 x i32> @llvm.x86.avx2.pmovsxwd(<8 x i16>) nounwind readnone
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declare <4 x i64> @llvm.x86.avx2.pmovsxwq(<8 x i16>) nounwind readnone
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;
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; Basic sign extension tests
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;
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define <4 x i32> @sse41_pmovsxbd(<16 x i8> %v) nounwind readnone {
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; CHECK-LABEL: @sse41_pmovsxbd
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; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: sext <4 x i8> %1 to <4 x i32>
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; CHECK-NEXT: ret <4 x i32> %2
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%res = call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %v)
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ret <4 x i32> %res
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}
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define <2 x i64> @sse41_pmovsxbq(<16 x i8> %v) nounwind readnone {
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; CHECK-LABEL: @sse41_pmovsxbq
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; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
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; CHECK-NEXT: sext <2 x i8> %1 to <2 x i64>
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; CHECK-NEXT: ret <2 x i64> %2
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%res = call <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8> %v)
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ret <2 x i64> %res
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}
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define <8 x i16> @sse41_pmovsxbw(<16 x i8> %v) nounwind readnone {
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; CHECK-LABEL: @sse41_pmovsxbw
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; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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; CHECK-NEXT: sext <8 x i8> %1 to <8 x i16>
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; CHECK-NEXT: ret <8 x i16> %2
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%res = call <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8> %v)
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ret <8 x i16> %res
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}
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define <2 x i64> @sse41_pmovsxdq(<4 x i32> %v) nounwind readnone {
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; CHECK-LABEL: @sse41_pmovsxdq
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; CHECK-NEXT: shufflevector <4 x i32> %v, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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; CHECK-NEXT: sext <2 x i32> %1 to <2 x i64>
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; CHECK-NEXT: ret <2 x i64> %2
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%res = call <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32> %v)
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ret <2 x i64> %res
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}
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define <4 x i32> @sse41_pmovsxwd(<8 x i16> %v) nounwind readnone {
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; CHECK-LABEL: @sse41_pmovsxwd
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; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: sext <4 x i16> %1 to <4 x i32>
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; CHECK-NEXT: ret <4 x i32> %2
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%res = call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %v)
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ret <4 x i32> %res
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}
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define <2 x i64> @sse41_pmovsxwq(<8 x i16> %v) nounwind readnone {
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; CHECK-LABEL: @sse41_pmovsxwq
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; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
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; CHECK-NEXT: sext <2 x i16> %1 to <2 x i64>
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; CHECK-NEXT: ret <2 x i64> %2
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%res = call <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16> %v)
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ret <2 x i64> %res
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}
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define <8 x i32> @avx2_pmovsxbd(<16 x i8> %v) nounwind readnone {
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; CHECK-LABEL: @avx2_pmovsxbd
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; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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; CHECK-NEXT: sext <8 x i8> %1 to <8 x i32>
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; CHECK-NEXT: ret <8 x i32> %2
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%res = call <8 x i32> @llvm.x86.avx2.pmovsxbd(<16 x i8> %v)
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ret <8 x i32> %res
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}
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define <4 x i64> @avx2_pmovsxbq(<16 x i8> %v) nounwind readnone {
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; CHECK-LABEL: @avx2_pmovsxbq
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; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: sext <4 x i8> %1 to <4 x i64>
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; CHECK-NEXT: ret <4 x i64> %2
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%res = call <4 x i64> @llvm.x86.avx2.pmovsxbq(<16 x i8> %v)
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ret <4 x i64> %res
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}
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define <16 x i16> @avx2_pmovsxbw(<16 x i8> %v) nounwind readnone {
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; CHECK-LABEL: @avx2_pmovsxbw
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; CHECK-NEXT: sext <16 x i8> %v to <16 x i16>
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; CHECK-NEXT: ret <16 x i16> %1
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%res = call <16 x i16> @llvm.x86.avx2.pmovsxbw(<16 x i8> %v)
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ret <16 x i16> %res
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}
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define <4 x i64> @avx2_pmovsxdq(<4 x i32> %v) nounwind readnone {
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; CHECK-LABEL: @avx2_pmovsxdq
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; CHECK-NEXT: sext <4 x i32> %v to <4 x i64>
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; CHECK-NEXT: ret <4 x i64> %1
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%res = call <4 x i64> @llvm.x86.avx2.pmovsxdq(<4 x i32> %v)
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ret <4 x i64> %res
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}
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define <8 x i32> @avx2_pmovsxwd(<8 x i16> %v) nounwind readnone {
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; CHECK-LABEL: @avx2_pmovsxwd
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; CHECK-NEXT: sext <8 x i16> %v to <8 x i32>
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; CHECK-NEXT: ret <8 x i32> %1
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%res = call <8 x i32> @llvm.x86.avx2.pmovsxwd(<8 x i16> %v)
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ret <8 x i32> %res
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}
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define <4 x i64> @avx2_pmovsxwq(<8 x i16> %v) nounwind readnone {
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; CHECK-LABEL: @avx2_pmovsxwq
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; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: sext <4 x i16> %1 to <4 x i64>
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; CHECK-NEXT: ret <4 x i64> %2
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%res = call <4 x i64> @llvm.x86.avx2.pmovsxwq(<8 x i16> %v)
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ret <4 x i64> %res
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}
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136
test/Transforms/InstCombine/x86-pmovzx.ll
Normal file
136
test/Transforms/InstCombine/x86-pmovzx.ll
Normal file
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@ -0,0 +1,136 @@
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; RUN: opt < %s -instcombine -S | FileCheck %s
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declare <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8>) nounwind readnone
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declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8>) nounwind readnone
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declare <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16>) nounwind readnone
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declare <8 x i32> @llvm.x86.avx2.pmovzxbd(<16 x i8>) nounwind readnone
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declare <4 x i64> @llvm.x86.avx2.pmovzxbq(<16 x i8>) nounwind readnone
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declare <16 x i16> @llvm.x86.avx2.pmovzxbw(<16 x i8>) nounwind readnone
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declare <4 x i64> @llvm.x86.avx2.pmovzxdq(<4 x i32>) nounwind readnone
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declare <8 x i32> @llvm.x86.avx2.pmovzxwd(<8 x i16>) nounwind readnone
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declare <4 x i64> @llvm.x86.avx2.pmovzxwq(<8 x i16>) nounwind readnone
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;
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; Basic zero extension tests
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;
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define <4 x i32> @sse41_pmovzxbd(<16 x i8> %v) nounwind readnone {
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; CHECK-LABEL: @sse41_pmovzxbd
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; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: zext <4 x i8> %1 to <4 x i32>
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; CHECK-NEXT: ret <4 x i32> %2
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%res = call <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8> %v)
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ret <4 x i32> %res
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}
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define <2 x i64> @sse41_pmovzxbq(<16 x i8> %v) nounwind readnone {
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; CHECK-LABEL: @sse41_pmovzxbq
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; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
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; CHECK-NEXT: zext <2 x i8> %1 to <2 x i64>
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; CHECK-NEXT: ret <2 x i64> %2
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%res = call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %v)
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ret <2 x i64> %res
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}
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define <8 x i16> @sse41_pmovzxbw(<16 x i8> %v) nounwind readnone {
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; CHECK-LABEL: @sse41_pmovzxbw
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; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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; CHECK-NEXT: zext <8 x i8> %1 to <8 x i16>
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; CHECK-NEXT: ret <8 x i16> %2
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%res = call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %v)
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ret <8 x i16> %res
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}
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define <2 x i64> @sse41_pmovzxdq(<4 x i32> %v) nounwind readnone {
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; CHECK-LABEL: @sse41_pmovzxdq
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; CHECK-NEXT: shufflevector <4 x i32> %v, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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; CHECK-NEXT: zext <2 x i32> %1 to <2 x i64>
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; CHECK-NEXT: ret <2 x i64> %2
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%res = call <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32> %v)
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ret <2 x i64> %res
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}
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define <4 x i32> @sse41_pmovzxwd(<8 x i16> %v) nounwind readnone {
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; CHECK-LABEL: @sse41_pmovzxwd
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; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: zext <4 x i16> %1 to <4 x i32>
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; CHECK-NEXT: ret <4 x i32> %2
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|
||||
%res = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %v)
|
||||
ret <4 x i32> %res
|
||||
}
|
||||
|
||||
define <2 x i64> @sse41_pmovzxwq(<8 x i16> %v) nounwind readnone {
|
||||
; CHECK-LABEL: @sse41_pmovzxwq
|
||||
; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
|
||||
; CHECK-NEXT: zext <2 x i16> %1 to <2 x i64>
|
||||
; CHECK-NEXT: ret <2 x i64> %2
|
||||
|
||||
%res = call <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16> %v)
|
||||
ret <2 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i32> @avx2_pmovzxbd(<16 x i8> %v) nounwind readnone {
|
||||
; CHECK-LABEL: @avx2_pmovzxbd
|
||||
; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: zext <8 x i8> %1 to <8 x i32>
|
||||
; CHECK-NEXT: ret <8 x i32> %2
|
||||
|
||||
%res = call <8 x i32> @llvm.x86.avx2.pmovzxbd(<16 x i8> %v)
|
||||
ret <8 x i32> %res
|
||||
}
|
||||
|
||||
define <4 x i64> @avx2_pmovzxbq(<16 x i8> %v) nounwind readnone {
|
||||
; CHECK-LABEL: @avx2_pmovzxbq
|
||||
; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; CHECK-NEXT: zext <4 x i8> %1 to <4 x i64>
|
||||
; CHECK-NEXT: ret <4 x i64> %2
|
||||
|
||||
%res = call <4 x i64> @llvm.x86.avx2.pmovzxbq(<16 x i8> %v)
|
||||
ret <4 x i64> %res
|
||||
}
|
||||
|
||||
define <16 x i16> @avx2_pmovzxbw(<16 x i8> %v) nounwind readnone {
|
||||
; CHECK-LABEL: @avx2_pmovzxbw
|
||||
; CHECK-NEXT: zext <16 x i8> %v to <16 x i16>
|
||||
; CHECK-NEXT: ret <16 x i16> %1
|
||||
|
||||
%res = call <16 x i16> @llvm.x86.avx2.pmovzxbw(<16 x i8> %v)
|
||||
ret <16 x i16> %res
|
||||
}
|
||||
|
||||
define <4 x i64> @avx2_pmovzxdq(<4 x i32> %v) nounwind readnone {
|
||||
; CHECK-LABEL: @avx2_pmovzxdq
|
||||
; CHECK-NEXT: zext <4 x i32> %v to <4 x i64>
|
||||
; CHECK-NEXT: ret <4 x i64> %1
|
||||
|
||||
%res = call <4 x i64> @llvm.x86.avx2.pmovzxdq(<4 x i32> %v)
|
||||
ret <4 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x i32> @avx2_pmovzxwd(<8 x i16> %v) nounwind readnone {
|
||||
; CHECK-LABEL: @avx2_pmovzxwd
|
||||
; CHECK-NEXT: zext <8 x i16> %v to <8 x i32>
|
||||
; CHECK-NEXT: ret <8 x i32> %1
|
||||
|
||||
%res = call <8 x i32> @llvm.x86.avx2.pmovzxwd(<8 x i16> %v)
|
||||
ret <8 x i32> %res
|
||||
}
|
||||
|
||||
define <4 x i64> @avx2_pmovzxwq(<8 x i16> %v) nounwind readnone {
|
||||
; CHECK-LABEL: @avx2_pmovzxwq
|
||||
; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; CHECK-NEXT: zext <4 x i16> %1 to <4 x i64>
|
||||
; CHECK-NEXT: ret <4 x i64> %2
|
||||
|
||||
%res = call <4 x i64> @llvm.x86.avx2.pmovzxwq(<8 x i16> %v)
|
||||
ret <4 x i64> %res
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user