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ARM: tblgen'erate more NEON two-operand aliases.

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VMUL and VEXT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155258 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2012-04-20 23:46:33 +00:00
parent 0b35c35efc
commit 8e3c17aabf
1 changed files with 12 additions and 39 deletions
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51
lib/Target/ARM/ARMInstrNEON.td
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@ -2395,6 +2395,8 @@ class N3VDSL<bits<2> op21_20, bits<4> op11_8,
[(set (Ty DPR:$Vd),
(Ty (ShOp (Ty DPR:$Vn),
(Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
// All of these have a two-operand InstAlias.
let TwoOperandAliasConstraint = "$Vn = $Vd";
let isCommutable = 0;
}
class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
@ -2405,6 +2407,8 @@ class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
[(set (Ty DPR:$Vd),
(Ty (ShOp (Ty DPR:$Vn),
(Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
// All of these have a two-operand InstAlias.
let TwoOperandAliasConstraint = "$Vn = $Vd";
let isCommutable = 0;
}
@ -2440,6 +2444,8 @@ class N3VQSL<bits<2> op21_20, bits<4> op11_8,
(ResTy (ShOp (ResTy QPR:$Vn),
(ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
imm:$lane)))))]> {
// All of these have a two-operand InstAlias.
let TwoOperandAliasConstraint = "$Vn = $Vd";
let isCommutable = 0;
}
class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
@ -2451,6 +2457,8 @@ class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
(ResTy (ShOp (ResTy QPR:$Vn),
(ResTy (NEONvduplane (OpTy DPR_8:$Vm),
imm:$lane)))))]> {
// All of these have a two-operand InstAlias.
let TwoOperandAliasConstraint = "$Vn = $Vd";
let isCommutable = 0;
}
@ -5299,6 +5307,9 @@ def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
// VEXT : Vector Extract
// All of these have a two-operand InstAlias.
let TwoOperandAliasConstraint = "$Vn = $Vd" in {
class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
: N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
(ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm,
@ -5318,6 +5329,7 @@ class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
bits<4> index;
let Inst{11-8} = index{3-0};
}
}
def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> {
let Inst{11-8} = index{3-0};
@ -5764,28 +5776,6 @@ defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
(VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
// VMUL two-operand aliases.
def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm$lane",
(VMULslv4i16 DPR:$Ddn, DPR:$Ddn, DPR_8:$Dm,
VectorIndex16:$lane, pred:$p)>;
def : NEONInstAlias<"vmul${p}.i16 $Qdn, $Dm$lane",
(VMULslv8i16 QPR:$Qdn, QPR:$Qdn, DPR_8:$Dm,
VectorIndex16:$lane, pred:$p)>;
def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm$lane",
(VMULslv2i32 DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
VectorIndex32:$lane, pred:$p)>;
def : NEONInstAlias<"vmul${p}.i32 $Qdn, $Dm$lane",
(VMULslv4i32 QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
VectorIndex32:$lane, pred:$p)>;
def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm$lane",
(VMULslfd DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
VectorIndex32:$lane, pred:$p)>;
def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Dm$lane",
(VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
VectorIndex32:$lane, pred:$p)>;
// VLD1 single-lane pseudo-instructions. These need special handling for
// the lane index that an InstAlias can't handle, so we use these instead.
def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr",
@ -6572,23 +6562,6 @@ def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
(VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
// Two-operand variants for VEXT
def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
(VEXTd8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_7:$imm, pred:$p)>;
def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
(VEXTd16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_3:$imm, pred:$p)>;
def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
(VEXTd32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_1:$imm, pred:$p)>;
def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
(VEXTq8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_15:$imm, pred:$p)>;
def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
(VEXTq16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_7:$imm, pred:$p)>;
def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
(VEXTq32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_3:$imm, pred:$p)>;
def : NEONInstAlias<"vext${p}.64 $Vdn, $Vm, $imm",
(VEXTq64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_1:$imm, pred:$p)>;
// Two-operand variants for VQDMULH
def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm",
(VQDMULHv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;